View TXC-03453B_414434.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SDH/SONET SIDE (TELECOM BUS)
Drop Bus
O-Bit Interfaces
External Alarm Interfaces
Control Signals
POH Interfaces
LINE SIDE
TL3M
Add Bus
Triple Level 3 Mapper TXC-03453B
Microprocessor Interface
Alarm Indication Port
Boundary Scan
U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096; 5,297,180; 5,289,507; 5,473,611; 5,535,218; 5,528,598; 6,463,111 B1 U.S. and/or foreign patents issued or pending Copyright (c) 2003 TranSwitch Corporation PHAST, TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation * 3 Enterprise Drive * Shelton, Connecticut 06484 Tel: 203-929-8810 * Fax: 203-926-9453 * www.transwitch.com
om .c 4U et he aS at .D w w w
Receive Interfaces (3) (Rail, NRZ) Transmit Monitor Interfaces (3) Transmit Interfaces (3) (Rail, NRZ)
Document Number: PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
*
USA
PRELIMINARY information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. Characteristic data and other specifications are subject to change. Contact TranSwitch Applications Engineering for current information on this product.
m o .c U t4 e e h S ta a .D w w w
APPLICATIONS
* Add/drop multiplexers * Digital cross connect systems * Transmission equipment * Broadband switching systems
Proprietary TranSwitch Corporation Information for use Solely by its Customers
om .c 4U et he FEATURES aS at .D w w w
TL3M Device
Triple Level 3 Mapper TXC-03453B DATA SHEET DESCRIPTION
Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal using a byte- wide parallel interface in the TranSwitch Telecom Bus format. The TL3M supports Drop bus and Add bus SDH/ SONET timing modes. Drop bus timing provides the timing signals for the add side. Timing for both buses is independent for the Add bus timing mode. Individual POH bytes are mapped into a RAM interface for microprocessor access and to an external interface for external processing if required. In the add direction (except for the B3 byte) POH bytes may be inserted individually from RAM locations, from the external interface, or from the local side/alarm indication port. An option is provided to generate an unequipped channel or AIS. An external interface is provided for accessing the O-bits. An alarm indication port is provided for ring operation. The TL3M also uses internal digital desynchronizers that have a built-in pointer leak algorithm. The line side can be configured for a NRZ or positive/negative rail interface. For testing purposes, the TL3M provides boundary scan, PRBS generators and analyzers, a BIP error mask, and DS3/E3 line and facility loopbacks. The TL3M provides either Motorola or Intel microprocessor access. The interrupt has programmable mask bits. A software polling register is also provided.
* Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 * SDH/SONET bus access: - Byte-wide drop and Add buses - Drop bus timing mode (Add bus timing derived from Drop bus) - Add bus timing mode (independent timing for drop/Add buses) * Path overhead byte processing: - Microprocessor access - External interface - B3 generation/detection with test mask - B3 bit/block performance counters - REI bit/block performance counters - C2 mismatch detection - C2 unequipped detection and generation * Alarm indication port - Path REI count and RDI status for APS applications * O-bit channel access via external interface * Digital desynchronizer with internal pointer leak algorithm * Line interface: - NRZ or P/N rail option for transmit and for receive - Monitor NRZ transmit data * Microprocessor access: - Motorola or Intel compatible - Hardware interrupt with mask bits - Software polling bits * Testing: - Facility or line loopback - PRBS generator/analyzer - Boundary scan (IEEE 1149.1 standard) * A fully tested device driver is available * 3.3 volt power supply, 5 volt tolerant inputs * 324-lead plastic ball grid array package (23 mm x 23 mm)
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
TABLE OF CONTENTS
Section Page
List of Figures ................................................................................................................................... 3 Features ........................................................................................................................................... 4 Application Examples ....................................................................................................................... 8 Block Diagram .................................................................................................................................. 9 Block Diagram Description ............................................................................................................. 10 Lead Diagram ................................................................................................................................. 15 Lead Descriptions ........................................................................................................................... 16 Absolute Maximum Ratings and Environmental Limitations ........................................................... 29 Thermal Characteristics .................................................................................................................. 29 Power Requirements ...................................................................................................................... 29 Input, Output and Input/Output Parameters ................................................................................... 30 Timing Characteristics .................................................................................................................... 32 Operation ........................................................................................................................................ 51 Digital Desynchronizer PLL Connections ................................................................................ 51 Transmit and Receive Synthesizer Connections ..................................................................... 51 Typical Test Results ................................................................................................................ 52 MTIE per GR-253-CORE Sec 5.7 ........................................................................................... 54 Testing .................................................................................................................................... 58 Boundary Scan ........................................................................................................................ 60 Memory Map .................................................................................................................................. 62 Package Information ...................................................................................................................... 90 Ordering Information ...................................................................................................................... 91 Related Products ............................................................................................................................ 91 Standards Documentation Sources ................................................................................................ 92 List of Data Sheet Changes ........................................................................................................... 94 Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are available from the Products page of the TranSwitch Web site at www.transwitch.com. Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 2 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
LIST OF FIGURES
Figure
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38.
Page
Typical Application using the TL3M and PHAST-3N Devices ........................................... 8 TL3M TXC-03453B Block Diagram ................................................................................... 9 TL3M Multiplexing Structure ............................................................................................ 10 SONET AU-3/STS-1 SPE Build Format .......................................................................... 12 ITU-T TUG-3 Build Format .............................................................................................. 13 TL3M TXC-03453B Lead Diagram .................................................................................. 15 Line Side Transmit Timing for Channel n ........................................................................ 32 Line Side Receive Timing for Channel n ......................................................................... 33 Line Side Receive Timing in Facility Loopback for Channel n ......................................... 34 STM-1 Add Bus Derived Interface Timing ....................................................................... 35 STS-3 Add Bus Derived Interface Timing ....................................................................... 36 STM-1 Drop Bus Interface Timing ................................................................................... 37 STS-3 Drop Bus Interface Timing ................................................................................... 38 STM-1 Add/Drop Bus Interface Timing ........................................................................... 39 STS-3 Add/Drop Bus Interface Timing ............................................................................ 40 Transmit Path Overhead Timing ..................................................................................... 41 Receive Path Overhead Timing ...................................................................................... 42 Transmit Alarm Indication Port Timing ............................................................................ 43 Receive Alarm Indication Port Timing ............................................................................. 44 Transmit Overhead Communications Channel Interface Timing ..................................... 45 Receive Overhead Communications Channel Interface Timing ...................................... 45 Intel Microprocessor Read Cycle Timing ......................................................................... 46 Intel Microprocessor Write Cycle Timing ......................................................................... 47 Motorola Microprocessor Read Cycle Timing ................................................................. 48 Motorola Microprocessor Write Cycle Timing .................................................................. 49 Boundary Scan Timing .................................................................................................... 50 Digital Desynchronizer External Component Connections .............................................. 51 Transmit and Receive Synthesizer External Component Connections ........................... 51 STS3/DS3 Mapping, Measured Jitter .............................................................................. 52 STM1/E3 Mapping, Measured Jitter ................................................................................ 53 STS-1 Pointer Movements on DS3 Payload ................................................................... 55 Jitter Tolerance for DS3 (from GR-499) .......................................................................... 56 Jitter Transfer for DS3 (GR-253) ..................................................................................... 56 Jitter Tolerance for E3 (ITU G.751 Fig. 2) ....................................................................... 57 Jitter Transfer for E3 (from ITU G.823 Fig. 15) ................................................................ 57 Per Channel Loopbacks and PRBS Test Generators/Analyzer ...................................... 59 Boundary Scan Schematic .............................................................................................. 61 TL3M TXC-03453B Package Diagram ............................................................................ 90
- 3 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
FEATURES
The TL3M supports the following features. Please note that the convention used here is that the transmit (or add) direction is from the DS3/E3 line signal (rail or NRZ) to the SDH/SONET format (Telecom Bus), while the receive (or drop) direction is from the SDH/SONET format to the DS3/E3 line. Bus Timing (Telecom Bus): The TL3M provides the following bus timing modes for the Telecom Bus modes of operation: * Drop bus timing * Add bus timing is derived from the Drop bus timing input signals * Drop bus: C1J1, SPE, optional C1, data, clock, and parity signals leads are inputs * Add bus: data, parity, and add indication signal leads are outputs * Add bus timing * Add bus timing is supplied and is independent of the Drop bus timing * Drop bus: C1J1, SPE, optional C1, data, clock and parity signal leads are inputs * Add bus: clock, C1J1, and SPE signal leads are inputs; data, parity, and add indication signal leads are outputs Mappings: The TL3M provides the following mapping features: * Maximum of three channels for either E3 or DS3 line signals * STM-1 AU-4 VC-4 format * Each E3 or DS3 signal into TUG-3 format * STS-3 format * Each DS3 signal into STS-1 format * Same drop and Add bus for all channels * Add bus contention indication (same channel assignment) * Add Bus: high impedance Add bus if there is contention * Broadcast mode * Drop Bus: multiple channel assignment to the same TUG-3 SDH/SONET Rates: The TL3M provides the following Telecom Bus rates and format mappings: * STS-3 STS-1s (19.44 Mbyte/s) * STM-1 VC-4 (19.44 Mbyte/s) Other Telecom Bus Features: The TL3M provides the following additional bus features: * SDH/SONET interface Drop bus * Input parity check with alarm monitoring * Odd parity * Bus signals * Input loss of clock detection * Stuck high or low * Loss of J1 reference
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 4 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
* Positive/negative justification count for J1 pulse * External path AIS and other alarm (e.g., LOP) indication * SDH/SONET interface Add bus * Output parity generation * Odd parity * Bus indication (active low to indicate bus activity) * Ability to High-Z the output bus signals * Under processor control * Input loss of clock detection * Stuck high or low SDH/SONET Processing Features * In-band upstream path AIS detection * TOH E1 bytes * Majority vote * TUG-3 pointer tracking * ETSI-based state machine * 8-bit PJ and NJ counters * NDF, LOP and AIS alarm detection , * TUG-3 pointer generation * Slaved to drop or Add bus J1 pulse * Adjusts pointer accordingly * POH byte processing (TUG-3, STS-1) * All receive POH bytes accessible * Microprocessor access * POH interface * J1 byte * 64-byte host processor read * B3 parity error check * Bit or block count * G1 byte * Single-bit RDI alarm detection with a 5 or 10 event option * REI (FEBE) counter (16 bits) * C2 byte * Signal label mismatch and unequipped detection * POH byte Insertion (TUG-3, STS-1) * All POH bytes * Microprocessor access * POH interface * Control bits to determine source of input bytes * J1 byte * 64-byte message
- 5 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
* G1 byte * Receive side or alarm indication port * REI (FEBE) insertion from B3 byte errors * Single-bit RDI insertion * C2 byte * Path label insertion * SDH/SONET AIS generation * TUG-3s * Unequipped channel generation * TUG-3s * Desynchronizer * Meets ITU, ETSI, and ANSI performance requirements * Pointer test sequence * Jitter * Internal * Digital * Internal pointer leak algorithm or microprocessor control O-Bit (Overhead Communications) Channel Access: * Microprocessor access (two-bit field) * Option for two reserved bits in the E3 format * External serial bit interface (clock and data) * Gapped clock * Asynchronous Line AIS Detection: * Transmit E3 AIS detection per ITU G.775 Line AIS Generation: * Transmit and receive sides * Generate as a result SDH/SONET alarms or line level alarms * Mask enable bits * Global enable bit * Microprocessor control Line Interface: * Rail interface * Clock, positive and negative rail signals * DS3/E3 loss of signal detection in transmit direction * BPV counter * DS3 B3ZS or E3 HDB3 codec function * Loss of clock detector * Invert clock polarity (receive and transmit)
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 6 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
* NRZ interface * Clock and data * Loss of Clock Detector * External interface for loss of signal (transmit direction) * Invert clock polarity (receive and transmit) * High-Z output leads * Receive Line Outputs * Transmit Monitor Outputs * Per channel control via host * Transmit Monitor Port * Clock and data Test Features: * Boundary Scan that meets IEEE 1149.1 standard * High-Z all output leads option * Loopbacks per channel * DS3/E3 line with generate receive AIS output option * DS3/E3 facility * Pseudo-random test generator and analyzer per channel * 215-1, or 223-1 * Uses CV counter to count errors * B3 BIP-8 error mask * RAM value substituted * Column error control Microprocessor Interface: * Microprocessor * Split address/data buses * Selectable Intel or Motorola Alarms And Interrupts: * Hardware interrupt option * Mask bits * Positive level * Software polling bit * Latched and unlatched alarms * Saturating or rollover counters option Device Driver: * Device configuration * Fault monitoring * Performance monitoring
- 7 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
APPLICATION EXAMPLES
The TL3M can be used in a wide range of telecommunications applications, such as: * * * * Add/drop multiplexers Digital cross connect systems Router systems Transmission systems
Note: Each bus contains a Drop bus and an Add bus
STM-1/STS-3 Serial I/O or Parallel I/O
PHAST-3N TXC-06103
TL3M TXC-03453B
Three Asynchronous E3 or DS3 Line Signals
B Bus Alarm Indication Ports A Bus Alarm Indication Ports
PHAST-3N STM-1/STS-3 Serial I/O or Parallel I/O TXC-06103
TL3M TXC-03453B
Three Asynchronous E3 or DS3 Line Signals
Figure 1. Typical Application using the TL3M and PHAST-3N Devices Figure 1 shows a Telecom Bus bidirectional E3/DS3 add/drop STM-1/STS-3 multiplexer. The three E3's or DS3's may be dropped from either direction with full time slot reuse in both directions. If required, the asynchronous line interfaces for the two TL3M devices may be tied together. An option is provided in which the output line interface can be forced to the high impedance state.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 8 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
BLOCK DIAGRAM
SDH/SONET SIDE
LINE SIDE
one of three channels
ISTAn PAISn
Note: n = 1 - 3 channels
RECEIVE
DCLK DC1J1 DSPE DC1 DD(7-0) DPAR DROP BLOCK DECODE BLOCK DESTUFF BLOCK DESYNC BLOCK OUTPUT BLOCK RPOSn RNEGn RCLKn
RnPOD RnPOF RnPOC TnPOD TnPOF TnPOC
PATH OVERHEAD INTERFACE BLOCK
RnAID AIP BLOCK TnAID TnAIC TnAIF
RnOCC RnOCD TnOCC TnOCD
O-BIT INTERFACE BLOCK
DS3/E3 AIS GENERATION BLOCK
DAISC EAISC
TRANSMIT
RnNRD ACLK AC1J1 ASPE ADD AD(7-0) APAR ADD BLOCK BUILD BLOCK STUFF/ SYNC BLOCK INPUT BLOCK RnNRC TPOSn TNEGn/LOSn TCLKn
RESET ABTIM TRI INTEL 8 10 PROCESSOR INTERFACE BLOCK D7 -D0 A9 - A0 SEL RD WR RDY INT MOTO=L RAMCI TCK BOUNDARY SCAN BLOCK TDI TRS TMS TDO MOTOROLA D7 -D0 A9 - A0 SEL RD/WR Tie high DTACK IRQ MOTO=H
INTERNAL RAM BLOCK
Figure 2. TL3M TXC-03453B Block Diagram
- 9 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
BLOCK DIAGRAM DESCRIPTION
A functional block diagram of the TL3M is shown in Figure 2. The portion of the ITU-T SDH multiplexing structure implemented by each Level 3 Mapper within the TL3M device is shown in Figure 3. Each of the three Level 3 mappers is multiplexed/demultiplexed from a SDH/SONET Telecom Bus interface which is carrying the three STS-3 STS-1s or STM-1 VC-4 TUG-3s.
xN STM-N AUG
x1 AU-4 VC-4
ITU-T SDH multiplexing structure C-4 One mapper of TL3M device x3 x1 TUG-3 x7 AU-3 VC-3 VC-4 TU-3 VC-3
139264 kbit/s (Note 1)
x3 Same as STS-3
44736 kbit/s or 34368 kbit/s (Note 1, 2) C-3
STS-1 x7 TUG-2 Pointer processing Multiplexing Aligning Mapping TU-11 VC-11 C-11 1544 kbit/s (Note 1) x4
x1 TU-2 x3 TU-12 VC-12 C-12 VC-2 C-2
6312 kbit/s (Note 1)
2048 kbit/s (Note 1)
Note 1: G.702 tributaries associated with containers C-x are shown. Other signals (e.g., ATM) can also be accommodated. Note 2: AU-3/VC-3 is for DS3 only.
Figure 3. TL3M Multiplexing Structure In the receive direction the drop side parallel Telecom Bus interface uses a bus signaling rate of 19.44 MHz. The parallel interface at the drop block consists of byte-wide input data (DD(7-0)), a C1J1 input indication (DC1J1), an SPE input indication (DSPE), input clock (DCLK), and input parity (DPAR). The C1 (J0) pulse, which is required, is used in conjunction with an active low SPE indication to determine the start of the SDH/ SONET frame. The J1 pulse (in the DC1J1 signal) and an active high SPE indication determine the starting location of the VC-4 within the STM-1 format and also the start of each of the STS-1s in the STS-3 format. There are three J1 pulses required for the STS-3 format, and a single J1 pulse required for the STM-1 VC-4 format. The Drop bus clock (DCLK) is also monitored for a stuck high or low state. The data leads and other bus leads are calculated for odd parity and compared against the incoming input parity lead (DPAR) to determine if there is a parity error. Other than a parity error indication, no action is taken by the TL3M. The C1J1 pulse is also monitored for a loss of J1 pulse. An option is provided in which the C1 pulse can be supplied on a separate lead from the DC1J1 lead (DC1 lead). The Decode block contains the logic for performing the pointer interpretation and tracking for each of the three TUG-3s, when the STM-1 VC-4 format is selected. The H1/H2 pointer bytes in each of the TUG-3s are monitored for loss of pointer, AIS, and a New Data Flag (NDF) indication. The pointer state machines are implemented using the algorithms specified in ETSI and ANSI documents. Performance counters are provided for justification events. The TL3M does not perform pointer tracking for the STS-1 signals, or for the VC-4 formats. Instead, the J1 indication is used as the start of format indication.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 10 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
This block also performs SDH/SONET E1 byte AIS detection, which may be carrying an upstream in-band AIS indication. The TranSwitch PHAST-3N and SOT-3 devices have an option to generate an in-band line/path AIS indication for the downstream mappers, such as the TL3M, which enables line AIS to be generated without having to perform an additional pointer AIS detection. In addition, two leads are provided for an out-of-band upstream AIS indication, using either the PAISn or ISTAn leads. The POH bytes from the TUG-3 or the STS-1 format are provided at the POH Interface block for external processing, if required. Each of the three mappers' POH interfaces consists of an output data lead (RnPOD), framing pulse (RnPOF) and a clock signal (RnPOC), where n represents each of three level 3 mappers, starting with channel 1. All the POH bytes in each of the STS-1s and TUG-3s are supplied, including the B3 byte. All POH bytes from each of the TUG-3s or STS-1s are also written into Internal RAM block segments for microprocessor access. In addition, the J1 byte is written into a 64-byte RAM segment on an arbitrary address rotating basis. Each mapper section also performs POH byte processing, which includes RDI detection, C2 mismatch detection and unequipped detection. The received O-bits for the DS-3 format are provided at the O-Bit Interface block and are also written into a 2-bit RAM location for microprocessor access. Two reserved bits in the E3 format have been designated as an O-bit channel, if required. The bits in the RAM location are updated each frame by the TL3M. There is no synchronous relationship between the SDH/SONET frame and the bits written into these RAM locations. The external interface consists of a serial data lead (RnOCD) and a clock lead (RnOCC). An Alarm Indication Port block is provided for ring configurations. The alarm indication port consists of a data lead (RnAID), which is used with the corresponding POH interface framing pulse (RnPOF) and clock signal (RnPOC). The information on the data lead consists of the REI count and the path RDI alarm summary status. In a ring configuration, this information is inserted from the mate TL3M mapper channel into the local TL3M mapper channel G1 byte for transmission. The Destuff block works in conjunction with the Desync block to remove the stuff columns in the payloads, and also performs the majority logic voting for the DS3 and E3 formats. The majority voting logic uses the justification control bits to determine if the S-bit (or bits) is carrying a stuffing state or data. The Desync block, using a digital desynchronizer, is responsible for removing the effects on the output of the DS3 or E3 signals of systemic jitter due to signal mapping and pointer movements. Each of the three desyncronizers has a built-in TranSwitch proprietary pointer leak algorithm, which is transparent to the user. An option is provided in which the pointer leak rate can be programmed by the host processor. The output has an average frequency equal to the source frequency and has jitter characteristics that meet both ITU and ANSI standards. A line DS3/E3 AIS generator is provided, which enables line AIS to be generated for the various upstream alarms, such as loss of pointer. A control bit is also provided which enables the microprocessor to send line AIS independent of the alarm states. An option is provided which enables line AIS to be generated when a channel is placed in line loopback. The Output block provides either a positive (RPOSn) and negative (RNEGn) rail line signal, or an NRZ line signal (RPOSn), and a clock signal (RCLKn). The receive E3 HDB3 and DS3 B3ZS coder operates independent of the transmitter side. A control bit is provided for inverting the clock output, if required. Also provided is a control bit which enables the receive data and clock leads to be forced to a high impedance state, independent of interface type (rail or NRZ) selected. This permits two interfaces from two different devices to be tied together for ring configurations. In the transmit direction (towards the Add bus), the Input block supports either a positive (TPOSn) and negative (TNEGn) rail line signal, or an NRZ line signal (TPOSn), and a clock signal (TCLKn). A control bit enables the transmit input clock to be inverted. The Input block performs either the E3 HDB3 or DS3 B3ZS decoder function. Bipolar violations are counted in a 16-bit counter. A choice of bipolar violation sequence detection is also provided. The rail interface also detects an E3 or DS3 loss of signal. The input clock is also monitored for a stuck high or low condition. When the NRZ interface is selected, the unused negative rail input lead can be used to clock in an external loss of signal (LOS) indication from a downstream codec. - 11 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Control bits are provided which enable line AIS to be sent when either a loss of signal or input clock failure is detected. A control bit also enables the microprocessor to send line AIS, independent of alarms. Separate NRZ data (RnNRD) and clock (RnNRC) output signals are also provided which may be used for monitoring. The line signal is connected to the Stuff/Sync block. This block basically consists of a FIFO into which the data is written from the line and is read out by a SDH/SONET clock which is either derived from the Add bus (i.e., Add bus timing), or from the Drop bus (i.e., Drop bus timing). The stuffing algorithm for the DS3 signal uses one set of five control bits (C-bits) with one stuffing opportunity bit (S-bit) for frequency justification per subframe (nine subframes). The E3 format uses five pairs of control bits (C1 and C2 bits) to control two stuff opportunity bits (S1 and S2) per subframe (one subframe per three rows for a total of three subframes per frame). FIFO underflow and overflow alarm indications are provided. Should an underflow or overflow condition occur, the FIFO will immediately reset to a preset value. The FIFO also tracks an incoming line signal having an average frequency deviation as high as 20 ppm, and can simultaneously accept the signal with up to 5 UI peak-topeak jitter (where 1 UI = 1/f). The Build block formats the data bits into either a SONET STS-3 STS-1 SPE format (see Figure 4) or an STM1 VC-4 TUG-3 format (see Figure 5). The STS-1 format has two stuff columns and payload plus a column of POH bytes, while the TUG-3 format consists of the payload, plus a column of POH bytes and H1/H2 pointer bytes. The TUG-3 pointer bytes define the start of the J1 POH byte within the TUG-3. A fixed pointer value of 6800 hex is used as the initial value when building a TUG-3 format. There are two levels of pointer movements in the TUG-3 build process. In either drop or add timing, the transmit pointer value will increment or decrement when there is an STM-1 VC-4 increment or decrement based on the relative position of the J1 pulse in the C1J1. The pointer movement for the TUG-3s will be in the opposite direction. This feature can be disabled.
DS3 44.736 Mbit/s Subframe Format (1 of 9)
POH 8R 8R RRC 5I 200I 8R 8R CCRRRRRR 208I 8R 8R CCRROORS 208I
1
2
3
30 31
32
59 60
61
87
1
J1 B3 C2 G1 F2 H4 Z3 Z4 Z5
30
59
87 1
9
AU-3/STS-1 SPE Format (87 x 9)
Figure 4. SONET AU-3/STS-1 SPE Build Format
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 12 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
DS3 44.736 Mbit/s Subframe Format (1 of 9)
POH 8R 8R RRC 5I 200I 8R CCRRRRRR 208I 8R CCRROORS 208I
1
85
E3 34.368 Mbit/s Subframe Format (1 of 3)
RRRRRRC1C2 RRRROOC1C2
P O H 1
C C C
C C A
24I 24I B 8I 85 A B
S2IIIIIII
RRRROORR RRRRRRRR
RRRRRRRS1
24I
24I
24I
24I
24I
24I
24I
24I
24I
C
1
24I
24I
24I
24I
24I
24I
24I
24I
24I
24I
85 Note: Normally the two O-bits in the E3 format are designated as Reserved. 1
H1 K3 H2 N1 H3 J1 B3 C2 G1 F2 H4 F3
86 1
9
TUG-3 Format (86 x 9)
Figure 5. ITU-T TUG-3 Build Format
- 13 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
An O-bit interface value or a value written into RAM by the microprocessor is mapped into the two O-bit positions in the DS3 format. The O-bit interface consists of an output clock signal (TnOCC) and an input data lead (TnOCD). The relationship between the O-bit channel and the SDH/SONET frame in both directions is asynchronous. The nine individual POH bytes (except the B3 byte) can be inserted into the TUG-3 or STS-1 POH bytes from values written to RAM by the microprocessor or from the transmit POH interface. The POH interface consists of an input data lead (TnPOD), output framing pulse (TnPOF), and an output clock signal (TnPOC), where n represents each of three level 3 mappers. A control bit enables the POH interface bytes to be written into RAM for microprocessor access when transmitted. In the case of the G1 byte, the value can also be inserted from the local receive side or from the alarm indication port. A test mask is provided for the calculated B3 byte, which permits up to eight errors to be transmitted. For ring operation, an alarm indication port is provided in the AIP block. The alarm indication port consists of an input data lead (TnAID), input framing pulse (TnAIF), and input clock signal (TnAIC). The information on the data lead consists of the REI count, and the path RDI alarm summary status. In ring operation, this information is inserted into the G1 byte for transmission. The Add block uses either the add or drop timing signals. Add bus timing is enabled by placing a high on control lead ABTIM. When Add bus timing is selected, the timing for the two buses, add and drop, is supplied by separate inputs for add and drop. When Add bus timing is selected, the output Add bus signals consist of bytewide data (AD(7-0)), add indication (ADD), and odd parity (APAR). The Add bus input timing signals consist of a 19.44 MHz clock (ACLK), C1J1 indication (AJ1C1) and a SPE active indication (ASPE). The output Add bus signals consist of byte-wide data (AD(7-0)), add indication (ADD), and odd parity (APAR). The active low add indication (ADD) indicates the location of all time slots being added to the Add bus. The Add bus clock is also monitored for a stuck high or low state when Add bus timing is selected. A bus contention alarm is provided if more than one channel is assigned to the same TUG-3 or STS-1. Drop bus timing is enabled by placing a low on control lead ABTIM. When Drop bus timing is selected, the timing for the Add bus depends upon the Drop bus input signals for operation. When Drop bus timing is selected, the output Add bus signals consist of byte-wide data (AD(7-0)), add indication (ADD), and odd parity (APAR). All of the control registers and performance counters, as well as the status and alarm indications, are accessible via a microprocessor interface. The TL3M supports either Intel or Motorola microprocessor bus interfaces, with hardware and software interrupts. Mask bits are provided for the latched status and alarm indications, to control whether each of them will generate an interrupt when active. The counters may be configured as either rollover or saturating. Saturating counters are cleared automatically when they are read. For board testing, boundary scan and the ability to force all the output signals to a high impedance state are provided. For network and device debugging, facility and line loopbacks are provided at the line interfaces. Each channel also has a PRBS test analyzer and generator (not shown in Figure 2).
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 14 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
LEAD DIAGRAM
BOTTOM VIEW
GND AB SUBS2 VDS2 AA VSS2 VRS2 Y VDS2 GRS2 W VDS2 V TSCK2 U TSET T TMOD R ACLK P AD0 N AD3 M AD4 L AD7 K DPAR DSPE DC1J1 J DD2 H DD3 G DD7 F SUBS1 GRS1 E SBS1 D VDS1 C VSS1 B GND R1AID A S1 R1OCD R1POF R2OCC R2POC NC R3OCD R3POF T1AIF NC T1POD T2AID T2AIF T2OCD T2POF T3AIC T3OCD T3POD IDD GND NC S2 TPLL R1POC NC R2OCD R2POF R3OCC R3POD T1AID T1OCC T1POC T2AIC T2OCC T2POC NC T3OCC DF1E T3POF ABTIM NC VSS1 VDS1 NC R1OCC R1POD R2AID R2POD R3AID R3POC T1AIC T1OCD T1POF TSCKT T2POD T3AID T3AIF T3POC NC TPOS1 NC RCLK1 VDS1 DD6 VDD NC NC VDD VDDC NC NC VDD VDDC NC NC VDD VDDC NC EXDCK VDD NC RPOS1 NC VSS1 NC NC RNEG1 R1NRD TNEG1 VSS1 VRS1 NC R2NRC R1NRC TCLK1 RNEG2 DD4 DD5 VDDC VDD RPOS2 RCLK2 R2NRD DD0 DD1 VDD VDDC DF2E TPOS2 TNEG2 NC GND GND GND GND GND GND VSD1 TCLK2 VSD1 VDD1 DC1 DCLK NC GND GND GND GND GND GND VSD1 VDD1 VSD1 SUBD1 AD5 AD6 VDDC GND GND GND GND GND GND VDD GRD1 DBS1 DF1B AD1 AD2 VDD GND GND GND GND GND GND VDDC VDD1 VRD1 DF1A AC1J1 ASPE NC GND GND GND GND GND GND VSD2 GRD2 VRD2 SUBD2 ADD NC APAR GND GND GND GND GND GND DBS2 VDD2 VSD2 VDD2 NC NC VDDC VDD VSD2 DF2B DF2A TSCK1 NC VDD VDDC VSD3 VDD2 VSD2 NC VSS2 NC NC DBS3 SUBD3 GRD3 VSS2 SBS2 NC NC VSD3 VSD3 VRD3 VSS2 VDD NC WR VDDC VDD RAMCI A0 VDDC VDD A7 NC VDDC VDD NC NC VDD RPOS3 VDD3 DF3A D3 ADD TSE3 D2 D6 RDY MOTO GND A1 A6 TSCK3 NC NC TDI TRS TPOS3 RCLK3 VDD3 VSD3 DF3B TSE1 TSE2 D1 D5 SEL RESET EAISC DAISC A2 A5 A9 PAIS1 PAIS2 PAIS3 TCK TDO DF3E R3NRD RNEG3 VDD3 SUB RPLL D0 D4 D7 RD INT GND GND A3 A4 A8 ISTA1 ISTA2 ISTA3 TRI TMS TCLK3 TNEG3 R3NRC GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Notes: 1. This is the bottom view. The leads are solder balls. See Figure 38 for package information. This view is rotated relative to the bottom view in Figure 38. 2. Lead symbols are described in the "Lead Descriptions" section. 3. Power supply leads are shown as solid black circles, ground leads as cross-hatched circles.
Figure 6. TL3M TXC-03453B Lead Diagram
- 15 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
LEAD DESCRIPTIONS
POWER SUPPLY, GROUND AND NO CONNECTS
Symbol VDDC
Lead No. D8, D12, D16, G4, H19, L4, M19, R4, T19, W7, W11, W15 D4, D7, D11, D15, D19, G19, H4, L19, M4, R19, T4, W4, W8, W12, W16, W19 C1, C3, D2 V1, W1, AA2 J22, K20, M20 P20, P22, T21 W21, Y20, AA22 J9 - J14 K9 - K14 L9 - L14 M9-M14 N9 - N14 P9 - P14 A1, Y10, A22, AB1, AB9, AB10, AB22 B1, C2, E3, F2 U3, V2, W3, Y1 J19, J21 K19, K21 N19, P21, R20, T22 T20, V20, V21, Y21 A8, A12, B2, B6, B17, B22, C4, C19, C21, D5, D6, D9, D10, D13, D14, D17, D20, D22, E4, E19, F4, J4, K4, N4, P3, R2, R3, T3, U2, U4, U19, V4, V19, W5, W14, W17, W18, Y14, Y15
I/O/P* P
Name/Function Core VDD: +3.3 volts, 5% power supply
VDD
VDD: +3.3 volts, 5% power supply
VDS1 VDS2 VDD1 VDD2 VDD3 GND
P P P P P P
VDD Analog: +3.3 volts, 5% power supply VDD Analog: +3.3 volts, 5% power supply VDD Analog: +3.3 volts, 5% power supply VDD Analog: +3.3 volts, 5% power supply VDD Analog: +3.3 volts, 5% power supply Core Ground: 0 volts reference
GND VSS1 VSS2 VSD1 VSD2 VSD3 NC
Ground: 0 volts reference P P P P P VSS (Analog Ground): 0 volts reference VSS (Analog Ground): 0 volts reference VSS (Analog Ground): 0 volts reference VSS (Analog Ground): 0 volts reference VSS (Analog Ground): 0 volts reference No Connect: NC leads are not to be connected, not even to another NC lead, but must instead be left floating. Connection of these leads may impair performance or cause damage to the device.
* Note: I = Input; O = Output; P = Power; T = Tristate:
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 16 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
DROP BUS INTERFACE Symbol DD(7-0) Lead No. F1, D3, G3, G2, G1, H1, H3, H2 I/O/P I Type* LVTTL Name/Function Drop Bus Data Byte: 19.44 Mbyte/s byte-wide data that corresponds to the STM-1 or STS-3 signal from the Drop bus. Lead F1 is DD7. Data that may be present on the bus, other than the TUG-3s, or the STS-3 STS-1 SPEs, is ignored. Drop Bus Clock: This clock operates at a 19.44 MHz rate. Drop bus byte-wide data (DD(7-0)), parity (DPAR), payload indicator (DSPE), and C1/J1 (DC1J1 and DC1) are clocked in on falling edges of this clock. This signal will provide timing for the add direction when the Drop bus timing mode is selected (lead ABTIM is low). DC1 K2 I LVTTL Drop C1 Pulse: External positive C1 pulse that may be provided on this lead instead of in the DC1J1 signal. This signal is internally or-gated with the DC1J1 signal to form a composite C1J1 signal. If this lead is not used it must be grounded. This signal will provide timing for the add direction when the Drop bus timing mode is selected (lead ABTIM is low). DC1J1 J3 I LVTTL Drop Bus C1 and J1 Indicator: The C1 pulse is an active high, one clock cycle-wide (DCLK) timing pulse that indicates the location of the first C1 (J0) time slot in the STM1 or STS-3 frame. If the C1 pulse is not present in this signal, it must be provided at the DC1 lead. One or three J1 pulses, also one clock cycle wide, identify the starting location of the J1 byte in the VC-4 format or the starting locations of the J1 bytes in each of the three STS-1s. This signal will provide timing for the add direction when the Drop bus timing mode is selected (lead ABTIM is low). DSPE J2 I LVTTL Drop Bus SPE Indicator: A signal that is active high during the STM-1 VC-4 format, and for each of the STS-3 STS-1 SPE periods. It is active low during the STS-3 TOH and STM-1 RSOH/MSOH byte times. This signal will provide timing for the add direction when the Drop bus timing mode is selected (lead ABTIM is low). DPAR J1 I LVTTL Drop Bus Parity Bit: Odd parity input for the data byte, the DSPE signal, and the composite DC1J1 pulse.
DCLK
K3
I
LVTTL
* Note: See the "Input, Output and Input/Output Parameters'' section for Type definitions.
- 17 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
ADD BUS INTERFACE Symbol AD(7-0) Lead No. K1, L3, L2, L1, M1, M3, M2, N1 I/O/P O(T) Type Name/Function
LVCMOS Add Bus Data Byte: 19.44 Mbytes/s byte-wide data that corresponds to the time slots that are placed on the Add 4mA bus by the TL3M. Lead K1 is AD7. The first bit transmitted (MSB) corresponds to bit 7. These leads are forced to a high impedance state when: - Data is not present - Hardware or software reset occurs - Drop Bus Loss Of Clock (DLOC) occurs when the Drop bus timing mode is selected (ABTIM lead is low) - When control bit ADDEN (bit 1 in 0C2H) is set to 0. LVTTL Add Bus Clock: This input clock operates at 19.44 MHz. The add clock is used when the Add bus timing mode is selected (ABTIM lead is high). Add bus byte-wide data (AD(7-0)), the ASPE signal, and the AC1J1 signal are clocked in on its falling edges. The parity (APAR) signal, and add indicator (ADD) are clocked out on its rising edges. This lead is disabled, and should be grounded, when the drop timing mode is selected (ABTIM lead is low). Add Bus SPE Indicator: An input signal that must be high to indicate the STM-1 VC-4 period, and each of the three STS-3/STS-1 SPE periods, when Add bus timing is selected. This lead is disabled, and should be grounded, when the drop timing mode is selected (ABTIM lead is low). Add Bus C1 and J1 Indicator: The C1 pulse is an active high, one clock cycle-wide (ACLK) input timing pulse that identifies the location of the first C1 (J0) time slot in the STM-1 or STS-3 frame. A single J1 pulse, also one clock cycle wide, identifies the starting location of the J1 byte in the STM-1 VC-4 signal. Three J1 pulses are used to identify the starting location of the J1 bytes in each of the three STS-3 STS-1 SPEs. This lead will carry only J1 pulse information when the DC1 lead is used. This lead is disabled, and should be grounded, when the drop timing mode is selected (ABTIM lead is low).
ACLK
P1
I
ASPE
N3
I
LVTTL
AC1J1
N2
I
LVTTL
ADD
P2
O
LVCMOS Add Indicator: An active low signal that identifies the position of the TUG-3 and STS-1 bytes that are being 4mA mapped to the Add bus. This signal will be high when - Data is not present - Hardware or software reset occurs - Drop Bus Loss Of Clock (DLOC) occurs when the Drop bus timing mode is selected (ABTIM lead is low) - When control bit ADDEN (bit 1 in 0C2H) is set to 0.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 18 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Symbol APAR
Lead No. P4
I/O/P O(T)
Type
Name/Function
LVCMOS Add Bus Parity Bit: This output bit represents an odd parity calculation for each data byte that is mapped to the 4mA Add bus in the add timing and Drop bus timing modes. This lead is forced to a high impedance state when - Data is not present - Hardware or software reset occurs - Drop Bus Loss Of Clock (DLOC) occurs when the Drop bus timing mode is selected (ABTIM lead is low) - When control bit ADDEN (bit 1 in 0C2H) is set to 0.
LINE INTERFACE Where n represents the channel (mapper) number, for channels 1 through 3. Symbol RPOS1 RPOS2 RPOS3 Lead No. D21 G20 W20 I/O/P* O (T) Type Name/Function
LVCMOS Receive Line Positive Rail/NRZ Data for Channel n: When control bit CODE (bit 6 in XC1H) is a 0 for the cor4mA responding channel, this lead provides the received NRZ output for the 44.736 (DS3) or 34.368 Mbit/s (E3) asynchronous line data. When control bit CODE is a 1, a positive rail output signal is provided. This lead is forced to a high impedance state when - Control bit L3EN (bit 0 in 0C2H) is set to 0 - Control bit L3OEN (bit 0 in XC2H) is set to 0 for the corresponding channel - Hardware reset (lead RESET) or software reset (RESETS, bit 0 in 0C7H) occurs - RESETn (bits 1-3 in 0C7H) is set to 1 for the corresponding channel. LVCMOS Receive Negative Rail Data for Channel n: When control bit CODE (bit 6 in XC1H) is a 0, the corresponding 4mA lead is set to low. When control bit CODE is a 1, a negative rail output is provided. This lead is forced to a high impedance state when - Control bit L3EN (bit 0 in 0C2H) is set to 0 - Control bit L3OEN (bit 0 in XC2H) is set to 0 for the corresponding channel - Hardware reset (lead RESET) or software reset (RESETS, bit 0 in 0C7H) occurs - RESETn (bits 1-3 in 0C7H) is set to 1 for the corresponding channel.
RNEG1 RNEG2 RNEG3
E20 F22 AA21
O (T)
- 19 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Symbol RCLK1 RCLK2 RCLK3
Lead No. C22 G21 Y19
I/O/P* O (T)
Type
Name/Function
LVCMOS Receive Line Clock for Channel n: The 44.736 or 4mA 34.368 Mbit/s line signals on the RPOSn/RNEGn signal leads are clocked out on falling edges of this clock when control bit INVCO (bit 4 in XC1H) is set to 0 for the corresponding channel. These signals are clocked out on rising edges when control bit INVCO is set to 1. This lead is forced to a high impedance state when - Control bit L3EN (bit 0 in 0C2H) is set to 0 - Control bit L3OEN (bit 0 in XC2H) is set to 0 for the corresponding channel - Hardware reset (lead RESET) or software reset (RESETS, bit 0 in 0C7H) occurs - RESETn (bits 1-3 in 0C7H) is set to 1 for the corresponding channel. LVTTL Transmit Line Positive Rail/NRZ Data: for Channel n. When control bit DECODE (bit 7 in XC1H) is set to 0 for the corresponding channel, this lead is used as the NRZ input for the 44.736 (DS3) or 34.368 Mbit/s (E3) asynchronous line signal. When control bit DECODE is a 1, the corresponding lead provides the positive rail data input for the internal decoder. Transmit Negative Rail Data or LOS Input: When control bit DECODE (bit 7 in XC1H) is a 1, the corresponding lead provides the negative rail data input for the internal decoder. When control bit DECODE is set to 0 for the corresponding channel, this lead can be used to input an external loss of signal alarm. If a lead is not used, it must be tied to ground. Transmit Line Clock: The NRZ or rail signal for a corresponding channel is clocked in on rising edges of this clock when control bit INVCI (bit 5 in XC1H) is set to 0. NRZ or rail data is clocked in on falling edges when control bit INVCI is set to 1.
TPOS1 TPOS2 TPOS3
C20 H21 Y18
I
TNEG1/ LOS1 TNEG2/ LOS2 TNEG3/ LOS3 TCLK1 TCLK2 TCLK3
E22 H22 AB20
I
LVTTL
F21 J20 AB19
I
LVTTL
R1NRD R2NRD R3NRD
E21 G22 AA20
O (T)
LVCMOS Monitor Transmit Line Data: Output provided for an optional external performance monitoring circuit. This 4mA serial NRZ output is provided after the line decoder in the transmit direction, and is independent of whether the transmit line input is configured for a NRZ or rail interface. Data is clocked out on rising edges of clock (RnNRC). This lead is forced to a high impedance state when - Control bit L3EN (bit 0 in 0C2H) is set to 0 - Control bit L3OEN (bit 0 in XC2H) is set to 0 for the corresponding channel - Hardware reset (lead RESET) or software reset (RESETS, bit 0 in 0C7H) occurs - RESETn (bits 1-3 in 0C7H) is set to 1 for the corresponding channel.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 20 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Symbol R1NRC R2NRC R3NRC
Lead No. F20 F19 AB21
I/O/P* O (T)
Type
Name/Function
LVCMOS Monitor Transmit Line Clock: Data (RnNRD) for the performance monitoring circuits is clocked out on rising 4mA edges of the corresponding clock. This lead is forced to a high impedance state when - Control bit L3EN (bit 0 in 0C2H) is set to 0 - Control bit L3OEN (bit 0 in XC2H) is set to 0 for the corresponding channel - Hardware reset (lead RESET) or software reset (RESETS, bit 0 in 0C7H) occurs - RESETn (bits 1-3 in 0C7H) is set to 1 for the corresponding channel.
OVERHEAD COMMUNICATIONS CHANNEL (O-BIT) INTERFACE Where n represents the channel number, channels 1 through 3. Symbol R1OCD R2OCD R3OCD Lead No. A4 B7 A9 I/O/P O Type Name/Function
LVCMOS Receive Overhead Communications Channel Data: Unaligned data output for the overhead communications 4mA channel (O-bits) defined in the DS3 format and two reserved bits defined in the E3 format are provided. The O-bits for channel n are clocked out on falling edges of the RnOCC clock signal. LVCMOS Receive Overhead Communications Channel Clock: A gapped 720 kHz output clock that has an average fre4mA quency of 144 kHz, that is used for clocking out the received overhead communications channel bits (RnOCD) to external circuitry. LVTTL Transmit Overhead Communications Channel Data: Data input for transmitting the overhead communications channel in the DS3 format, and two defined reserved bits in the E3 format. This input is enabled when a 1 is written to control bit EXOO (bit 7 in XC4H) for the corresponding channel. Data is clocked in on rising edges of the TnOCC clock signal. The bits are transmitted unaligned regarding bit position and subframe number within the payload.
R1OCC R2OCC R3OCC
C5 A6 B9
O
T1OCD T2OCD T3OCD
C12 A16 A19
I
T1OCC T2OCC T3OCC
B12 B15 B18
O
LVCMOS Transmit Overhead Communications Channel Clock: A gapped 720 kHz output clock that has an average fre4mA quency of 144 kHz, which is used for clocking in the transmit overhead communications channel bits (TnOCD) from external circuitry when enabled.
- 21 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
PATH OVERHEAD BYTE INTERFACE Where n represents the channel number, channels 1 through 3. Symbol R1POD R2POD R3POD Lead No. C6 C8 B10 I/O/P O Type Name/Function
LVCMOS Receive Path Overhead Byte Data: These leads provide a serial output for the nine path overhead bytes 4mA associated with each of the three TUG-3s or STS-1s. The nine POH bytes are clocked out on falling edges of the corresponding clock signal (RnPOC). LVCMOS Receive Path Overhead Byte Framing: A positive one 4mA (RnPOC) clock cycle-wide output framing pulse that is synchronous to the J1 byte location in the receive path overhead data signal (RnPOD). This signal is also used as the framing pulse for the receive alarm indication port output data signal (RnAID). LVCMOS Receive Path Overhead Byte Clock: A gapped clock used for clocking out the receive path overhead bytes 4mA (RnPOD), and receive alarm indication port data (RnAID) for each channel. LVTTL Transmit Path Overhead Byte Data: A serial input for the following path overhead bytes: J1, C2, G1, F2, H4, F3, K4, and N1 bytes. The POH bytes are clocked in on rising edges of the clock signal (TnPOC). The bit times corresponding to the B3 byte are ignored.
R1POF R2POF R3POF
A5 B8 A10
O
R1POC R2POC R3POC T1POD T2POD T3POD
B5 A7 C10 A13 C15 A20
O
I
T1POF T2POF T3POF T1POC T2POC T3POC
C13 A17 B20 B13 B16 C18
O
LVCMOS Transmit Path Overhead Byte Framing: A positive one (TnPOC) clock cycle-wide output framing pulse that 4mA determines the start of the J1 byte in transmit path overhead byte data signal (TnPOD). LVCMOS Transmit Path Overhead Byte Clock: A gapped output clock used for clocking in the transmit path overhead 4mA bytes from an external circuit.
O
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 22 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
ALARM INDICATION PORT Where n represents the channel number, channels 1 through 3 Symbol R1AID R2AID R3AID Lead No. A2 C7 C9 I/O/P O Type Name/Function
LVCMOS Receive Alarm Indication Port Data: Serial output leads that provide a 4-bit REI (FEBE) count based on the 4mA received B3 error count, and a Path RDI alarm indication for a mate TL3M device in a ring configuration, from each channel. These leads are normally connected to the corresponding Transmit alarm indication port data leads (TnAID) at the mate TL3M device. The receive path overhead byte clock (RnPOC) signal is used to clock out this signal. The receive path overhead frame signal (RnPOF) provides the frame reference. The bits are sent according to the following format and are repeated every eight bit times. Bit 1 is the MSB and is the first bit sent. Bits 1 2 3 4 5 RDI 6 0 7 0 8 1
REI Count T1AID T2AID T3AID B11 A14 C16 I LVTTL
Transmit Alarm Indication Port Data: These serial input leads are normally connected to the receive alarm indication port data output leads (RnAID) at the mate TL3M device for a ring configuration. Provides an input for the four bit REI count (received B3 error count), and the Path RDI alarm indication. The format is shown above. Transmit Alarm Indication Port Clock: These clock input leads are normally connected to the receive path overhead byte clock output leads (RnPOC) at the mate TL3M device for a ring configuration. Transmit alarm indication port data (TnAID) is clocked in on rising edges of TnAIC. Transmit Alarm Indication Port Framing Pulse: Normally connected to receive path overhead byte framing pulse output leads (RnPOF) at the mate TL3M device for a ring configuration. Used to indicate the location of the first bit in the byte.
T1AIC T2AIC T3AIC
C11 B14 A18
I
LVTTL
T1AIF T2AIF T3AIF
A11 A15 C17
I
LVTTL
- 23 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
ADDITIONAL SIGNALS Symbol DAISC Lead No. AA10 I/O/P I Type LVTTL Name/Function DS3 AIS Clock Input: Input clock for the DS3 AIS generator. This clock must be present for the DS3 AIS generator to function. The clock must have the operating line rate of 44.736 MHz, and a frequency stability of 20 ppm. This clock is also used as a backup clock for the transmit and receive PRBS generators in DS3 applications, in the event that the transmit or receive DS3 signal clocks are absent. Clock duty cycle of 45 to 55% is required. If this clock input is not used, it should be grounded. E3 AIS Clock Input: Input clock for the E3 AIS generator. This clock must be present for the E3 AIS generator to function. The clock must have the operating line rate of 34.368 MHz, and a frequency stability of 20 ppm. This clock is also used as a backup clock for the transmit and receive PRBS generators in E3 applications, in the event that the transmit or receive E3 signal clocks are absent. Clock duty cycle of 45 to 55% is required. If this clock input is not used, it should be grounded. Add Bus Timing Mode: A high placed on this lead selects the Add bus timing mode. In Add bus timing mode, Drop and Add buses function with independent timing. A low placed on this lead selects Drop bus timing mode. In this mode of operation, the Drop bus signals provide timing information for the add (transmit) section. Hardware Reset: A low clears all counters, presets internal logic, and forces the Add bus output signals and line interfaces to a high impedance state for all three channels. The reset signal must be low for a minimum of 200 nanoseconds. The bus clocks, line clocks, and microprocessor clock must also be present during the reset signal. This lead is provided with an internal pull-up resistor. External Path AIS Indication: A high on this lead may be used to indicate an external Path AIS has occurred. It causes the XPAIS status bit (bit 0 in XB4H/XB5H) to be set to 1. This lead is enabled when control bit XALM2AIS (bit 7 in XC2H) is a 1. When enabled, the in-band upstream AIS indication provided via the TOH E1 byte is disabled. If a lead is not used it should be grounded. External STS-1 Alarm Indication: A high on this lead may be used to indicate an external SDH/SONET alarm has occurred. It causes the XISTAT status bit (bit 1 in XB4H/XB5H) to be set to 1. If a lead is not used it should be grounded. High Impedance Enable: A low causes all TL3M digital outputs and bidirectional leads to be set to a high impedance state for board testing. This lead is provided with an internal pull-up resistor.
EAISC
AA9
I
LVTT
ABTIM
B21
I
LVTTL
RESET
AA8
I
LVTTLp
PAIS1 PAIS2 PAIS3
AA14 AA15 AA16
I
LVTTL
ISTA1 ISTA2 ISTA3 TRI
AB14 AB15 AB16 AB17
I
LVTTL
I
LVTTLp
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 24 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
DIGITAL DESYNCHRONIZERS Symbol DF1A DF1B Lead No. M22 L22 I/O/P I Type Analog Name/Function Digital Desynchronizer PLL External Capacitor Channel 1: An external 1.0 F 10% capacitor (alternate capacitor value 4.7 F) is connected between the two leads, as shown in the PLL connections diagram (Figure 27). Digital Desynchronizer PLL External Capacitor Channel 2: An external 1.0 F 10% capacitor (alternate capacitor value 4.7 F) is connected between the two leads, as shown in the PLL connections diagram (Figure 27). Digital Desynchronizer PLL External Capacitor Channel 3: An external 1.0 F 10% capacitor (alternate capacitor value 4.7 F) is connected between the two leads, as shown in the PLL connections diagram (Figure 27). Digital Desynchronizer PLL Bias Components Channel 1: An external 30.1 k 1% resistor is connected between the GRD1 lead and the DBS1 lead, as shown in the PLL connections diagram (Figure 27). VRD1 should be left unconnected. Digital Desynchronizer PLL Bias Components Channel 2: An external 30.1 k 1% resistor is connected between the GRD2 lead and the DBS2 lead, as shown in the PLL connections diagram (Figure 27). VRD2 should be left unconnected. Digital Desynchronizer PLL Bias Components Channel 3: An external 30.1 k 1% resistor is connected between the GRD3 lead and the DBS3 lead, as shown in the PLL connections diagram (Figure 27). VRD3 should be left unconnected. Digital Desynchronizer Dedicated Substrate Connections. These leads are normally connected to ground.
DF2A DF2B
R22 R21
I
Analog
DF3A DF3B
W22 Y22
I
Analog
VRD1 DBS1 GRD1
M21 L21 L20
I
Analog
VRD2 DBS2 GRD2
N21 P19 N20
I
Analog
VRD3 DBS3 GRD3
V22 U20 U22
I
Analog
SUBD1 SUBD2 SUBD3 DF1E DF2E DF3E
K22 N22 U21 B19 H20 AA19
I
Analog
O
LVCMOS FIFO Reset Indication. These leads are used to indicate a reset condition from their corresponding desynchro4mA nizer. The indication will be high for a minimum of 125 microseconds and a maximum of 250 microseconds for any of the following - Hardware Reset (RESET lead goes low) - RESET (bit 0 in 0C7H) is a 1 - RESETn (0C7H) is set to 1 for the corresponding channel. - FIFO overflow or underflow
- 25 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
TRANSMIT AND RECEIVE SYNTHESIZERS Symbol VRS1 SBS1 GRS1 Lead No. F3 D1 E2 I/O/P I Type Analog Name/Function Transmit Synthesizer Bias Components: An external 30.1 k 1% resistor is connected between the GRS1 lead and the SBS1 lead. A 220 pF bypass capacitor is connected between the SBS1 node and ground, as shown in the Synthesizer connections diagram (Figure 28). VRS1 should be left unconnected. Receive Synthesizer Bias Components: An external 30.1 k 1% resistor is connected between the GRS2 lead and the SBS2 lead. A 220 pF bypass capacitor is connected between the SBS2 node and ground, as shown in the Synthesizer connections diagram (Figure 28). VRS2 should be left unconnected. Dedicated Substrate Connections: These leads are normally connected to ground.
VRS2 SBS2 GRS2
Y2 V3 W2
I
Analog
SUBS1 SUBS2
E1 AA1
I
Analog
MICROPROCESSOR INTERFACE
Symbol A(9-0)
Lead No. AA13, AB13, W13, Y12, AA12, AB12, AB11, AA11, Y11, W10 AB6, Y7, AA6, AB5, Y3, Y6, AA5, AB4 W6
I/O/P I
Type LVTTL
Name/Function Address Bus: Used by the microprocessor for accessing a specific memory location in the TL3M for a read/write cycle. A9 is defined as the most significant bit (lead AA13).
D(7-0)
I/O
LVTTL/ Data Bus: Bidirectional data lines used for transferring LVCMOS data between the TL3M and the external microprocessor. D7 (lead AB6) is defined as the most significant bit. 8mA LVTTL Write (I mode): Intel Mode - An active low signal generated by the microprocessor for writing to the TL3M. Motorola Mode - Not used. This lead should be tied high. Read (I mode) or Read/Write (M mode): Intel Mode - An active low signal generated by the microprocessor for reading the TL3M memory map. Motorola Mode - A high signal generated by the microprocessor for reading the TL3M memory map. A low signal is used for writing to the TL3M. Select: A low enables data transfers between the microprocessor and the TL3M during a read/write cycle.
WR
I
RD or RD/WR
AB7
I
LVTTL
SEL
AA7
I
LVTTLp
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 26 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Symbol RDY/ DTACK
Lead No. Y8
I/O/P O (T)
Type
Name/Function
LVCMOS Ready (I mode) or Data Transfer Acknowledge (M mode): 8mA Intel Mode - A high is an acknowledgment from the addressed memory map location that the transfer can be completed. A low indicates that the TL3M has not completed the transfer cycle, and the microprocessor must wait before latching read data or completing the write cycle. Motorola Mode - During a read cycle, a low signal indicates the information on the data bus is valid. During a write cycle, a low signal acknowledges the acceptance of data. LVCMOS Interrupt: Intel Mode - A high on this output lead signals an inter4mA rupt request to the microprocessor (active high). Motorola Mode - A low on this lead signals an interrupt request to the microprocessor (active low). The interrupt lead state is also controlled by the control bit states listed in the following table INTZN (OC2H, bit 3) X 0 INTEN Interrupt Lead (OC2H, bit 2) 0 High impedance state 1 Interrupt lead held to the high-z state only when inactive 1 Interrupt lead enabled for normal operation
INT/IRQ
AB8
O (T)
1 RAMCI W9 I LVTTL
RAM Clock Input: Clock input for the internal RAM. This clock supports an arbitrator function for accessing the internal RAM structure. This clock must operate between 19 and 35 MHz with a duty cycle of (5010) percent. This clock and the microprocessor timing signals may operate asynchronously with respect to each other. Motorola/Intel Microprocessor Select: A high selects the Motorola microprocessor compatible bus interface. A low selects the Intel microprocessor compatible bus interface.
MOTO
Y9
I
LVTTL
- 27 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
BOUNDARY SCAN Symbol TDO TDI TCK Lead No. AA18 Y16 AA17 I/O/P O(T) I I Type Name/Function
LVCMOS Boundary Scan Test Data Output: Serial data clocked out on falling edges of TCK. 4mA LVTTLp LVTTL Boundary Scan Test Data Input: Serial data input for boundary scan test messages. Boundary Scan Test Clock: The input clock for boundary scan testing. The TDI and TMS states are clocked in on its rising edges. Boundary Scan Test Mode Select: The signal present on this lead is used to control test operations. Boundary Scan Test Reset: This lead must be asserted low for at least 250 nanoseconds in order to reset the TL3M device's Test Access Port (TAP) controller. The TAP controller may also be reset by holding the TMS signal lead high for at least five clock cycles of TCK. In applications which will not be using the boundary scan feature, this lead must be tied low, thereby holding the TAP controller reset.
TMS TRS
AB18 Y17
I I
LVTTLp LVTTLp
TRANSWITCH TEST LEADS Symbol TPLL Lead No. B4 I/O/P Type Name/Function
I/O
LVTTL/ Test Lead - Transmit PLL: Do not connect. LVCMOS 8mA LVTTL/ Test Lead - Receive PLL: Do not connect. LVCMOS 8mA LVTTLp LVTTL LVTTLp Test Lead: Do not connect. Test Lead: Tie lead to ground. Test Lead: Do not connect.
RPLL
AB3
I/O
IDD EXDCK TMOD TSE1 TSE2 TSE3 TSET TSCK1 TSCK2 TSCK3 TSCKT S1 S2 SUB ADD
A21 D18 R1 AA3 AA4 Y5 T1 T2 U1 Y13 C14 A3 B3 AB2 Y4
I I I I
LVTTLpd Test Leads: These leads must be grounded.
I
LVTTLpd Test Leads: These leads must be grounded.
O
LVCMOS Test Leads: These leads provide test outputs when enabled. Do not connect. 4mA
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 28 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage DC input voltage Storage temperature range Ambient Operating Temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit ESD Classification Symbol VDD VIN TS TA ME RH RH ESD Min -0.3 -0.5 -55 -40 5 30 0 60 100 Max +3.9 +5.5 150 +85 Unit V V
o
Conditions Note 1 Note 1 Note 1 0 ft/min linear airflow per EIA/JEDEC JESD22-A112-A Note 2 non-condensing Note 3
C
oC
Level % % V
absolute value 2000
Notes: 1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability. 2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied. 3. Test method for ESD per MIL-STD-883E, Method 3015.7.
THERMAL CHARACTERISTICS
Parameter Thermal resistance: junction to ambient Min Typ Max 23 Unit
oC/W
Test Conditions 0 ft/min linear airflow
POWER REQUIREMENTS
Parameter VDD IDD Power Dissipation, PDD Min 3.15 Typ 3.30 318 1050 1320 Max 3.45 Unit V mA mW At max VDD, -40 to +85oC (see Note 1) Test Conditions
Note 1. Maximum power dissipation does not show strong temperature dependency.
- 29 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
INPUT, OUTPUT AND INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS FOR LVTTL Parameter VIH VIL Input leakage current Input capacitance -10 5.0 Min 2.0 0.8 +10 Typ Max Unit V V A pF Test Conditions 3.15 VDD 3.45 3.15 VDD 3.45 0 to 5.25 V input
INPUT PARAMETERS FOR LVTTLp (LVTTL WITH INTERNAL PULL-UP) Parameter VIH VIL Input leakage current Input capacitance -100 5.0 Min 2.0 0.8 0.0 Typ Max Unit V V A pF Test Conditions 3.15 VDD 3.45 3.15 VDD 3.45 0 to 5.25 V input
INPUT PARAMETERS FOR LVTTLpd (LVTTL WITH INTERNAL PULL-DOWN) Parameter VIH VIL Input leakage current Input capacitance 0.0 5.0 Min 2.0 0.8 100 Typ Max Unit V V A pF Test Conditions 3.15 VDD 3.45 3.15 VDD 3.45 0 to 5.25 V input
OUTPUT PARAMETERS FOR LVCMOS 4mA Parameter VOH VOL IOL IOH Leakage Tristate Output Capacitance tRISE tFALL -10 7.5 10 10 4.0 -4.0 +10 Min VDD - 0.5 0.4 Typ Max Unit V V mA mA A pF ns ns CLOAD = 15pF CLOAD = 15pF 0 to 5.25 V input Test Conditions VDD = 3.15; IOH = -4.0 VDD = 3.15; IOL = 4.0
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 30 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
OUTPUT PARAMETERS FOR LVCMOS 8mA Parameter VOH VOL IOL IOH Leakage Tristate Output Capacitance tRISE tFALL -10 7.5 10 5.0 8.0 -8.0 +10 Min VDD - 0.5 0.4 Typ Max Unit V V mA mA A pF ns ns CLOAD = 25pF CLOAD = 25pF 0 to 5.25 V input Test Conditions VDD = 3.15; IOH = -8.0 VDD = 3.15; IOL = 8.0
INPUT/OUTPUT PARAMETERS FOR LVTTL/LVCMOS 8mA Parameter VIH VIL Input leakage current Input capacitance VOH VOL IOL IOH tRISE tFALL 8.0 -8.0 10 5.0 VDD - 0.5 0.4 -10 7.0 Min 2.0 0.8 +10 Typ Max Unit V V A pF V V mA mA ns ns CLOAD = 25pF CLOAD = 25pF VDD = 3.15; IOH = -8.0 VDD = 3.15; IOL= 8.0 Test Conditions 3.15 VDD 3.45 3.15 VDD 3.45 0 to 5.25 V input
- 31 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
TIMING CHARACTERISTICS
Detailed timing diagrams for the TL3M device are illustrated in Figures 7 through 26, with values of the timing intervals tabulated below the diagrams. All output times are measured with a maximum 25 pF load capacitance. Timing parameters are measured at voltage levels of (VIH + VIL)/2 for input signals or (VOH + VOL)/2 for output signals. Figure 7. Line Side Transmit Timing for Channel n
tCYC(1) TCLKn (INPUT) tSU TPOSn (INPUT) tSU LOSn (TNEGn) (INPUT) tSU TPOSn/TNEGn (INPUT) tH tH NRZ Interface Optional External LOS Indication (NRZ mode) tPWH(1) tH NRZ Interface
Rail Interface
tCYC(2) RnNRC (OUTPUT) tOD RnNRD (OUTPUT) Monitor Interface tPWH(2) Monitor Interface
Note:
Shown for control bit INVCI (bit 5 in XC1H) equal to 0; data is clocked in on the falling edge when INVCI equals 1. RnNRD is always clocked out on the rising edges of RnNRC. The delay between the input clock TCLKn and output clock RnNRC is not specified.
Parameter TCLKn clock period TCLKn duty cycle, tPWH(1)/tCYC(1) TPOSn/TNEGn setup time before TCLKn TPOSn/TNEGn hold time after TCLKn RnNRC clock period RnNRC duty cycle, tPWH(2)/tCYC(2) RnNRD output delay after RnNRC Note 1: 22.35 ns (DS3) or 29.10 ns (E3).
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Symbol tCYC(1) -tSU tH tCYC(2) -tOD
Min
Typ See Note 1
Max
Unit ns
40 2.0 3.0
50
60
% ns ns
See Note 1 40 0.0 50 60 5.0
ns % ns
- 32 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 8. Line Side Receive Timing for Channel n
tCYC RCLKn (OUTPUT) tOD RPOSn (OUTPUT) tOD RPOSn/RNEGn (OUTPUT) Rail Interface NRZ Interface tPWH
Note:
Shown for control bit INVCO (bit 4 in XC1H) equal to 0; data is clocked out on the rising edge when control bit INVCO equals 1. The three signals for all channels are forced to a high impedance state when control bit L3EN (bit 0 in 0C1H) is set to 0, or when a hardware or software reset occurs. Each channel's output is forced to a high impedance state when control bit L3OEN (bit 0 in XC2H) is set to 0.
Parameter RCLKn clock period RCLKn duty cycle, tPWH/tCYC RPOSn/RNEGn data output delay after RCLKn
Note 1. 22.35 ns (DS3) or 29.10 ns (E3).
Symbol tCYC --tOD
Min
Typ See Note 1
Max
Unit ns
45 0.0
50
55 2.0
% ns
- 33 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 9. Line Side Receive Timing in Facility Loopback for Channel n
tCYC RCLKn (OUTPUT) tOD RPOSn (OUTPUT) tOD RPOSn/RNEGn (OUTPUT) Rail Interface NRZ Interface tPWH
Note:
Control bit INVCO (bit 4 in XC1H) has no effect on which edge the data is transmitted. The three signals for all channels are forced to a high impedance state when control bit L3EN (bit 0 in 0C1H) is set to 0, or when a hardware or software reset occurs. Each channel's output is forced to a high impedance state when control bit L3OEN (bit 0 in XC2H) is set to 0. Facility loopback is enabled when control bit FLBK (bit 2 in XC1H) is set to 1.
Parameter RCLKn clock period RCLKn duty cycle, tPWH/tCYC RPOSn/RNEGn data output delay after RCLKn edge (same relation as on TCLKn to TPOSn/ TNEGn in facility loopback).
Note 1: 22.35 ns (DS3) or 29.10 ns (E3).
Symbol tCYC --tOD
Min
Typ See Note 1
Max
Unit ns
45 0.0
50
55 4.0
% ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 34 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 10. STM-1 Add Bus Derived Interface Timing
tCYC tPWH ACLK (INPUT) tSU(2) ASPE (INPUT) tH(1) AC1J1 (INPUT) AD(7-0) APAR (OUTPUTS) ADD (OUTPUT) tSU(1) C1(1) J1 tOD(1) tOD(3) tH(2)
DATA
STUFF BYTE FOR J1
H1 TUG-3
t tOD(4) OD(2)
Note:
The relationship between the J1 and the SPE signals is shown for illustration purposes only. For the STM-1 format, there will be one J1 pulse, which indicates the start of the VC-4 that carries the three TUG-3s. The TUG-3 added to the bus is shown for the TUG-3 designated as A. TUG3 B will occur one clock cycle later. TUG-3 C will occur two clock cycles later. There is always a one byte delay between the AC1J1/ASPE input signals and the AD(7-0) output leads.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1 setup time before ACLK AC1J1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK AD(7-0) and APAR output delay from ACLK ADD low output delay from ACLK AD(7-0) and APAR tristate delay from ACLK ADD high output delay from ACLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 1.0 4.0 1.0 4.0 5.0 7.0 6.0 5.0
50
60
% ns ns ns ns
12.0 13.0 14.0 12.0
ns ns ns ns
- 35 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 11. STS-3 Add Bus Derived Interface Timing
tCYC tPWH ACLK (INPUT) tSU(2) ASPE (INPUT) tH(1) AC1J1 (INPUT) AD(7-0) APAR (OUTPUTS) ADD (OUTPUT) tSU(1) C1(1)
J1 for STS-1 #1 DATA STS-1#1 J1 for STS-1 #2 J1 STS1#1 J1 for STS-1 #3 DATA STS-1#1
tH(2) tOD(1) tOD(3)
tOD(4) tOD(2)
Note:
The relationship between the J1 and the SPE signals is shown for illustration purposes only. For the STS-3 format, there will be three J1 pulses, which indicate the start of each of the STS-1 SPEs. The STS-1 SPE added to the bus is shown for STS-1 number 1. STS-1 number 2 will occur one clock cycle later. STS-1 number 3 will occur two clock cycles later. There is always a one byte delay between the AC1J1/ASPE input signals and the AD(7-0) output leads.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1 setup time before ACLK AC1J1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK AD(7-0) and APAR output delay from ACLK ADD low output delay from ACLK AD(7-0) and APAR tristate delay from ACLK ADD high output delay from ACLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 1.0 4.0 1.0 4.0 5.0 7.0 6.0 5.0
50
60
% ns ns ns ns
12.0 13.0 14.0 12.0
ns ns ns ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 36 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 12. STM-1 Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tH DD(7-0) DPAR (INPUTS) DSPE (INPUT) tSU DC1J1 (INPUT) tH
C1(1)
J1
tSU
C1(1) C1(2) C1(3) J1 FIXED STUFF FIXED STUFF H1(1) TUG-3 H1(2) TUG-3
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STM-1 format, there will be one J1 pulse which indicates the start of the VC-4 that carries the three TUG-3s. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DD(7-0) data/DPAR/DC1J1/DC1/DSPE setup time before DCLK DD(7-0) data/DPAR/DC1J1/DC1/DSPE hold time after DCLK
Symbol tCYC -tSU tH
Min
Typ 51.44
Max
Unit ns
40 4.0 4.0
50
60
% ns ns
- 37 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 13. STS-3 Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tH DD(7-0) DPAR (INPUTS) DSPE (INPUT) tSU DC1J1 (INPUT) tH
C1(1)
J1 for STS-1#1 J1 for STS-1#2 J1 for STS-1#3
tSU
C1(1) C1(2) C1(3) J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3 DATA STS-1 #1
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STS-3 format, there will be three J1 pulses which indicate the start of each of the STS-1 SPEs. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DD(7-0) data/DPAR/DC1J1/DC1/DSPE setup time before DCLK DD(7-0) data/DPAR/DC1J1/DC1/DSPE hold time after DCLK
Symbol tCYC -tSU tH
Min
Typ 51.44
Max
Unit ns
40 4.0 4.0
50
60
% ns ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 38 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 14. STM-1 Add/Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU(1) DD(7-0) DPAR (INPUTS) DSPE (INPUT) tSU(1) DC1J1 (INPUT)
C1(1)
C1(1) C1(2)
tH(1)
C1(3) DATA DATA DATA J1
FIXED STUFF FIXED STUFF
H1(1) TUG-3
H1(2) TUG-3
tH(2) tSU(2)
tH(1)
J1
tOD(1) AD(7-0) APAR (OUTPUTS)
DATA
FIXED STUFF FOR J1
tOD(2)
tOD(3)
ADD (OUTPUT)
tOD(4)
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STM-1 format, there will be one J1 pulse which indicates the start of the VC-4 that carries the three TUG-3s. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded. Shown is TUG-3 A being added to the Add bus.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DD(7-0) data/DPAR/DC1J1/DC1 setup time before DCLK DD(7-0) data/DPAR/DC1J1/DC1 hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK AD(7-0) data and APAR delay after DCLK ADD indicator delay after DCLK AD(7-0) and APAR tristate delay after DCLK ADD high delay after DCLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 4.0 4.0 1.0 4.0 5.0 7.0 6.0 5.0
50
60
% ns ns ns ns
15.0 15.0 15.0 12.0
ns ns ns ns
- 39 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 15. STS-3 Add/Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU(1) DD(7-0) DPAR (INPUTS) DSPE (INPUT) tSU(1) DC1J1 (INPUT)
C1(1)
C1(1) C1(2)
tH(1)
C1(3) DATA DATA DATA J1
FIXED STUFF FIXED STUFF
tH(2) tSU(2)
tH(1)
J1 for STS-1#1
J1 for STS-1#2
J1 for STS-1#3
AD(7-0) APAR (OUTPUTS) ADD (OUTPUT)
tOD(1)
DATA
J1 DATA
tOD(3)
tOD(2)
tOD(4)
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STS-3 format, there will be three J1 pulses with each J1 pulse indicating the start of an STS-1. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded. Shown is STS-1 number 1 being added to the Add bus.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DD(7-0)/DPAR/DC1J1/DC1 setup time before DCLK DD(7-0)/DPAR/DC1J1/DC1 hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK AD(7-0) data and APAR delay after DCLK ADD indicator delayed after DCLK AD(7-0) data and APAR tristate after DCLK ADD indicator high after DCLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 4.0 4.0 1.0 4.0 5.0 7.0 6.0 5.0
50
60
% ns ns ns ns
15.0 15.0 15.0 12.0
ns ns ns ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 40 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 16. Transmit Path Overhead Timing
tPWL tPWH TnPOC (OUTPUT)
tPWH
tD tPW tSU tH
TnPOF (OUTPUT)
TnPOD (INPUT)
Bit 1 J1 Bit 2 J1 Bit 3 J1 Bit 4 J1 Bit 5 J1 Bit 6 J1 Bit 7 J1 Bit 8 J1 Bit 1 B3
Note: The clock cycle that corresponds to bit 8 in each overhead byte is stretched.
Parameter TnPOC high time TnPOC low time TnPOF output delay after TnPOC TnPOD setup time before TnPOC TnPOD data hold time after TnPOC TnPOF pulse width
Symbol tPWH tPWL tD tSU tH tPW
Min 617
Typ
Max 3395
Unit ns ns
772 -1.0 15.0 1.0 1389 2.0
ns ns ns ns
- 41 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 17. Receive Path Overhead Timing
tPWL tPWH RnPOC (OUTPUT)
tPWL
tD(1) tPW tD(2)
RnPOF (OUTPUT)
RnPOD (OUTPUT)
Bit 8 Z5
Bit 1 J1
Bit 2 J1
Bit 3 J1
Bit 4 J1
Bit 5 J1
Bit 6 J1
Bit 7 J1
Bit 8 J1
Bit 1 B3
Note: The clock cycle that corresponds to bit 8 in each overhead byte is stretched.
Parameter RnPOC low time RnPOC high time RnPOF output delay after RnPOC RnPOD output delay after RnPOC RnPOF pulse width
Symbol tPWL tPWH tD(1) tD(2) tPW
Min 617
Typ
Max 3395
Unit ns ns
772 0.0 0.0 1389 2.0 2.0
ns ns ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 42 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 18. Transmit Alarm Indication Port Timing
tPWL tPWH TnAIC (INPUT) tSU(1) TnAIF (INPUT) tSU(2) TnAID (INPUT)
Bit 1 Byte1 Bit 2 Byte 1 Bit 3 Byte 1 Bit 4 Byte 1 Bit 5 Byte 1 Bit 6 Byte 1 Bit 7 Byte 1
tPWL
tH(1)
tH(2)
Bit 8 Byte 1
Bit 1 Byte 2
Note:
The alarm indication byte consists of eight bits and it is repeated nine times. Bit 8 in each byte is stretched. The first four bits correspond to the REI count to be transmitted (bits 1 through 4 in G1), bit 5 is the path RDI value to be transmitted, and bits 6 and 7 are set to 0, while bit 8 is set to 1.
Parameter TnAIC low time TnAIC high time TnAIF setup time before TnAIC TnAIF hold time after TnAIC TnAID setup time before TnAIC TnAID hold time after TnAIC
Symbol tPWL tPWH tSU(1) tH(1) tSU(2) tH(2)
Min 617
Typ
Max 3395
Unit ns ns ns ns ns ns
772 2.0 1.0 2.0 1.0
- 43 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 19. Receive Alarm Indication Port Timing
tPWL tPWH RnPOC (OUTPUT) tD(1) RnPOF (OUTPUT) tD(2) RnAID (OUTPUT)
tPWL
tPW
Bit 8 Byte 9
Bit 1 Byte 1 Bit 2 Byte 1
Bit 3 Byte 1 Bit 4 Byte 1
Bit 5 Byte 1
Bit 6 Byte 1
Bit 7 Byte 1
Bit 8 Byte 1
Bit 1 Byte 2
Note:
The alarm indication byte consists of eight bits and it is repeated nine times. Bit 8 in each byte is stretched. The first four bits correspond to the REI count (bits 1 through 4 in G1) based on the received B3 byte errors, bit 5 is the path RDI value to be transmitted based on received alarm indications, and bits 6 and 7 are set to 0, while bit 8 is set to 1.
Parameter RnPOC low time RnPOC high time RnPOF output delay after RnPOC RnAID output delay after RnPOC RnPOF pulse width
Symbol tPWL tPWH tD(1) tD(2) tPW
Min 617
Typ
Max 3395
Unit ns ns
772 0.0 0.0 1389 2.0 2.0
ns ns ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 44 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 20. Transmit Overhead Communications Channel Interface Timing
tPWL TnOCC (OUTPUT) tPWH tH tSU TnOCD (INPUT)
Parameter TnOCC high time TnOCC low time TnOCD setup time before TnOCC TnOCD hold time after TnOCC
Symbol tPWH tPWL tSU tH
Min
Typ 772
Max
Unit ns
617 18.0 0.0
11900
ns ns ns
Figure 21. Receive Overhead Communications Channel Interface Timing
tPWL RnOCC (OUTPUT) tD tPWH
RnOCD (OUTPUT)
Parameter RnOCC high time RnOCC low time RnOCD output delay after RnOCC
Symbol tPWH tPWL tD
Min
Typ 772
Max
Unit ns
4646 0.0
7700 3.5
ns ns
- 45 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 22. Intel Microprocessor Read Cycle Timing
A (9-0) tH(1) D(7-0) tD(1) tSU(1) tF(1)
SEL tSU(2) RD tPW(1) tH(2)
tF(2)
tD(2) RDY
tD(3) tPW(2)
Parameter A(9-0) address hold time after RD A(9-0) address setup time before SEL D(7-0) data valid delay after RDY D(7-0) data float time after RD RD pulse width SEL setup time before RD SEL hold time after RD RDY delay after SEL RDY delay after RD RDY pulse width (See Note 1) RDY float time after SEL
Symbol tH(1) tSU(1) tD(1) tF(1) tPW(1) tSU(2) tH(2) tD(2) tD(3) tPW(2) tF(2)
Min 4.0 0.0
Typ
Max
Unit ns ns
13.0 13.0 40.0 10.0 0.0 16.0 14.0 0.0 48 * Rcyc 12.5
ns ns ns ns ns ns ns s ns
Note 1: RDY goes low when the address being read corresponds to a RAM location but remains high during status or control register access. RCYC is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25MHz yields tPW(2) = 1.92 s max).
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 46 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 23. Intel Microprocessor Write Cycle Timing
tH(1) A(9-0)
tH(2) D(7-0) tSU(2) tSU(1) SEL tSU(3) WR tD(1) RDY tPW(2) tD(2) tPW(1) tF tSU(4)
Parameter A(9-0) address hold time after WR A(9-0) address setup time before SEL D(7-0) data valid setup time before WR D(7-0) data hold time after WR SEL setup time before WR WR pulse width RDY delay after SEL RDY delay after WR RDY pulse width (See Note 1) RDY float time after SEL RAM cycle D(7-0) valid setup time before WR (See Note 1)
Symbol tH(1) tSU(1) tSU(2) tH(2) tSU(3) tPW(1) tD(1) tD(2) tPW(2) tF tSU(4)
Min 4.0 0.0 4.0 3.0 10.0 40.0
Typ
Max
Unit ns ns ns ns ns ns
16.0 15.0 0.0 48 * Rcyc 13.0 -2 * Rcyc
ns ns ns ns ns
Note 1: RDY goes low when the address being written to corresponds to a RAM location but remains high during status or control register access. RCYC is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25 MHz yields: tSU(4)= -80 ns min, tPW(2) = 1.92 s max).
- 47 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 24. Motorola Microprocessor Read Cycle Timing
tH(1) A(9-0)
D(7-0) tSU(1) tF(1) tPW(1) tSU(2) RD/WR tD(1) tPW(2) DTACK tD(2) tF(2) tH(3)
SEL
Parameter A(9-0) address hold time after SEL A(9-0) address valid setup time before SEL D(7-0) data valid delay after DTACK D(7-0) data float time after SEL SEL pulse width RD/WR setup time before SEL RD/WR hold time after SEL DTACK delay after SEL DTACK pulse width (See Note 1) DTACK float time after SEL
Symbol tH(1) tSU(1) tD(1) tF(1) tPW(1) tSU(2) tH(3) tD(2) tPW(2) tF(2)
Min 5.0 2.0
Typ
Max
Unit ns ns
4.0 15.0 40.0 5.0 5.0 15.0 0.0 48 * Rcyc 11.0
ns ns ns ns ns ns s ns
Note 1: RCYC is the period, in nanoseconds, of the RAM clock (RAMCI). (e.g., RAMCI @ 25 MHz yields tPW(2) = 1.92 s max).
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 48 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 25. Motorola Microprocessor Write Cycle Timing
tH(1) A(9-0) tH(2) D(7-0) tSU(2) tSU(4) SEL tSU(1) tSU(3) RD/WR
tPW(1) tH(3)
tPW(2) DTACK tD
tF
Parameter A(9-0) address hold time after SEL A(9-0) address valid setup time before SEL D(7-0) data valid setup time before SEL D(7-0) data hold time after SEL SEL pulse width RD/WR setup time before SEL RD/WR hold time after SEL DTACK delay after SEL DTACK pulse width (See Note 1) DTACK float time after SEL RAM cycle D(7-0) valid setup time before SEL (See Note 1)
Symbol tH(1) tSU(1) tSU(2) tH(2) tPW(1) tSU(3) tH(3) tD tPW(2) tF tSU(4)
Min 5.0 2.0 6.5 5.0 40.0 5.0 5.0
Typ
Max
Unit ns ns ns ns ns ns ns
15.0 0.0 48 * Rcyc 11.0 -2 * Rcyc
ns ns ns ns
Note 1: Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI). (e.g., RAMCI @ 25 MHz yields: tSU(4)= -80 ns min, tPW(2) = 1.92 s max).
- 49 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 26. Boundary Scan Timing
tPWL tPWH TCK (Input) tH(1) tSU(1) TMS (Input) tH(2) tSU(2) TDI (Input)
tD TDO (Output)
High-Z
tPW(1)
TRS (Input)
Parameter TCK clock high time TCK clock low time TMS setup time before TCK TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO output delay after TCK TRS pulse width
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tD tPW(1)
Min 50.0 50.0 3.0 2.0 3.0 4.0 250
Max
Unit ns ns
15.0
ns ns ns ns ns ns
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 50 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
OPERATION
DIGITAL DESYNCHRONIZER PLL CONNECTIONS The following diagram shows the external connections required for each of the three digital desynchronizers, where n defines the channels 1 through 3. Figure 27. Digital Desynchronizer External Component Connections
TL3M - Channels 1, 2, 3
VRDn (leads M21, N21, V22) DBSn (leads L21, P19, U20) 30.1 K 1% GRDn (leads L20, N20, U22) DFnA (leads M22, R22, W22) 1.0 F 10%* DFnB (leads L22, R21, Y22) * Preferred: 1.0 F, 10V ceramic X7R 1206. Alternate: 4.7 F, 6.3V ceramic X5R 1206. SUBDn (leads K22, N22, U21)
No Connection
Traces should be kept as short as possible. Place the external components as close as possible to the associated device leads. Please refer to AN-537 (TXC-03453-AN1) for additional recommendations for board layout design. This Application Note is available on the TL3M page of the TranSwitch web site, www.transwitch.com.
TRANSMIT AND RECEIVE SYNTHESIZER CONNECTIONS The following diagram shows the external connections required for the two synthesizer circuits.
Figure 28. Transmit and Receive Synthesizer External Component Connections
TL3M, n = 1, 2
No Connection
VRSn (leads F3, Y2) SBSn (leads D1, V3)
GRSn (leads E2, W2) 220 pF 10V, Ceramic X7R 0603 30.1 K 1% SUBSn (leads E1, AA1)
Traces should be kept as short as possible. Place the external components as close as possible to the associated device leads. Please refer to AN-537 (TXC-03453-AN1) for additional recommendations for board layout design. This Application Note is available on the TL3M page of the TranSwitch web site, www.transwitch.com.
- 51 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
TYPICAL TEST RESULTS Output Jitter
Test Condition
Maximum Measured Jitter (UIpp) at RCLKn output
Jitter Limit Specified by Telcordia GR-253 Ed. 3 Sept. 2000 (UIpp) Required Range See note 3 Objective Range N/A N/A N/A N/A 1.0 N/A N/A 1.3 N/A N/A 1.5 N/A N/A N/A N/A N/A
Mapping Jitter Single Pointer Adjustment Pointer Adjustment Burst Phase Transient Pointer Adjustment Burst Periodic Pointer Adjustments (87-3 sequence)
0.094 0.137 0.204 0.170 0.402 (T = 7.5ms) 0.282 (T = 34ms) 0.117 (T = 6s)1
0.4 0.094 + 0.3 1.3 1.2 N/A 1.0 1.0 N/A 1.3 1.3 N/A 1.0 1.0 1.3 1.3 1.3
Periodic Pointer Adjustments with added or canceled pointer adjustments (43-44 or 86-4 sequence) Periodic Pointer Adjustments Continuous Pattern
0.589 (T = 7.5ms) 0.423 (T = 34ms) 0.128 (T = 6s) 1 0.255 (T = 4ms) 0.231 (T = 34ms) 0.125 (T = 10s)
Periodic Pointer Adjustments Continuous Pattern with added or canceled Pointer Adjustments
0.380 (T = 18ms) 2 0.275 (T = 34ms) 0.122 (T = 10s)
Figure 29. STS3/DS3 Mapping, Measured Jitter
Notes for Figure 29: 1: W&G ANT20 Max. interval = 6.66S 2: W&G ANT20 Min interval = 15mS 3: Valid for DS3 mapped up to +/-45ppm 4: Data errors never occurred during the tests; 5) A low jitter COMBUS reference clock is required 5: Jitter measured with standard filters: HP=10 Hz, LP=400 kHz
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 52 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Test Condition Fig. 15-3/G.783
Maximum Measured Jitter (UIpp) at RCLKn output HP1/LP HP2/LP 0.045 0.054 0.050 0.050 0.044
Jitter Limit Specified by ITU-T G.783 ETSI EN 300 417-1-1 V1.1.3 (UIpp) See Note 2 HP1/LP 0.4 0.4 0.4 0.4 0.75 HP2/LP 0.075 0.075 0.075 0.075 0.075
Mapping Jitter Sequence A Sequence B Sequence C Sequence D
0.063 0.063 0.078 0.099 0.059
Figure 30. STM1/E3 Mapping, Measured Jitter Notes for Figure 30: 1: Data errors never occurred during the tests 2: Valid for E3 mapped up to +/-55ppm 3: A low jitter COMBUS reference clock is required 4: These measurements represent both AU-4 or TU-3 pointer movements for the SDH mappings 5: HP1=100 Hz, HP2=10 kHz, LP=800 k
- 53 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
MTIE PER GR-253-CORE SEC 5.7 Observation Time, S 0.1 Sec. Test Condition (GR-253-CORE) MTIE (nS) Limit (nS) 1.0 Sec. MTIE (nS) 9.0 Limit (nS) 170 10 Sec. MTIE (nS) 50 Limit (nS) 170 100 Sec. MTIE (nS) 160 Limit (nS) 170
Single STS-1 Pointer Adjustment (Note 1) 95 Phase Variation, Pointer spacing T=100S (GR-253-CORE Fig. 5-38) Maximum Rate Pointer Burst Phase Variation (GR-253-CORE Fig. 5-39) Phase Transient Pointer Burst Phase Variation (GR-253-CORE Fig. 5-40) 5.0 182
18
510
53
510
150
510
4.0
165
12
1155
60
1155
100
1155
Periodic STS-1 Pointer Adjustment 22 Phase Variation, 87-3 Pattern at T=4mS (beyond objective range, GR-253-CORE Fig. 5-42). Periodic STS-1 Pointer Adjustment 12 Phase Variation, 87-3 Pattern at T=100mS (GR-253-CORE Fig. 542). Periodic STS-1 Pointer Adjustment 9.0 Phase Variation, Continuous Pattern at T=7.5mS (objective range, GR-253-CORE Fig. 5-42). Periodic STS-1 Pointer Adjustment 10 Phase Variation, Continuous Pattern at T=34mS (GR-253-CORE Fig. 5-42). Periodic STS-1 Pointer Adjustment 7.0 Phase Variation, Continuous Pattern at T=100mS (GR-253-CORE Fig. 5-42). Periodic STS-1 Pointer Adjustment 4.0 Phase Variation, Continuous Pattern at T=1S (GR-253-CORE Fig. 5-42).
183
42
800
43
800
50
800
183
105
800
210
800
210
800
183
22
800
30
800
30
800
183
30
800
50
800
50
800
183
43
800
70
800
70
800
183
12
800
110
800
180
800
Note 1: Minimum observation is 1 Sec. since sample rate was set to 1 Sec. General measurement note: Min. MTIE interval is 0.1 Sec., Max 100 Sec. per GR-253-CORE
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 54 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Observation Time, S 0.1 Sec. Test Condition (GR-253-CORE) MTIE (nS) Limit (nS) 183 1.0 Sec. MTIE (nS) 22 Limit (nS) 800 10 Sec. MTIE (nS) 25 Limit (nS) 800 100 Sec. MTIE (nS) 90 Limit (nS) 800
Periodic STS-1 Pointer Adjustment 11 Phase Variation, Continuous Pattern at T=10S (GR-253-CORE Fig. 5-42).
Note 1: Minimum observation is 1 Sec. since sample rate was set to 1 Sec. General measurement note: Min. MTIE interval is 0.1 Sec., Max 100 Sec. per GR-253-CORE Figure 31. STS-1 Pointer Movements on DS3 Payload
- 55 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Figure 32. Jitter Tolerance for DS3 (from GR-499)
Figure 33. Jitter Transfer for DS3 (GR-253)
Note: At frequencies above 30 KHz, the TL3M exceeds the Jitter Transfer Mask because the applied jitter is attenuated below the generated jitter level. The generated jitter is well within the specification. This result is consistent with limitations of the test equipment and open-ended nature of the specification (-20dB slope with no plateau).
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 56 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 34. Jitter Tolerance for E3 (ITU G.751 Fig. 2)
Figure 35. Jitter Transfer for E3 (from ITU G.823 Fig. 15) - 57 of 96 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
TESTING Loopbacks Facility and line loopback capabilities are provided for each channel. Their operations are shown in Figure 36. Diagrams illustrating these two loopback modes are provided in the Memory Map section at Address XC1, Bits 2 and 1. Writing a 1 to control bit FLBK (Bit 2) enables facility loopback. When facility loopback is enabled, the internal DS3/E3 transmit signal becomes the internal receive signal. Either transmit line interface may be used, positive/negative rail or NRZ. Line loopback is enabled by writing a 1 to control bit L3LBK (Bit 1). The DS3/E3 receive output becomes the transmit line input. The receive line output may be positive/negative rail or NRZ. AIS will be sent as the received data when control bit LLBAIS (bit 0 in register 0C4H) is a 1. When control bit LLBAIS is set to 0, receive data is provided at the rail or NRZ interface.
Test Generators and Analyzers Two pseudo-random binary sequence (PRBS) test generators are provided for each channel, one in the receive direction and the other in the transmit direction, as shown in Figure 36. The generators provide either a 215-1 or 223-1 pseudo-random pattern using a common control bit. The selection of the PRBS pattern is also common with the PRBS test analyzer. The test sequence of 223-1 is selected when a 1 is written into control bit PAT23 (bit 4 in register XC6H). When control bit PAT23 is 0, the pattern is 215-1. The transmit test generator is enabled by writing a 1 to control bit TPRBS (bit 1 in register XC6H). When enabled, the transmit test generator inserts the selected pseudo-random pattern in place of the line signal. The transmit test generator uses the clock signal provided at the Transmit Line Clock (TCLK) input lead in order to function. The receive test generator is enabled by writing a 1 to control bit RPRBS (bit 0 in register XC6H). When enabled, the receive test generator inserts the pseudo-random test pattern in place of the received desynchronized NRZ data. The test analyzer is enabled by writing a 1 to control bit ENANA (bit 3 in register XC6H). Receive NRZ data is analyzed when a 0 is written to control bit TXANA (bit 2 in register 0C6H). When a 1 is written to control bit TXANA, the transmit NRZ data path is monitored. The selection of the test analyzer disables the decoder coding violation count to the 16-bit CV counter in registers XAEH and XAFH. Instead, this 16-bit counter is configured to count PRBS test analyzer errors when in lock.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 58 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 36. Per Channel Loopbacks and PRBS Test Generators/Analyzer
TLAISGN
DS3/E3 AIS GEN
DAISC, EAISC
CLK* L3LBK 0
Line In (TX DS3/E3)
To Synchronizer
1 0 1 0 TX PRBS GEN
DAISC, EAISC
LOS DET
1 Facility Loopback
TXANA TPRBS 1 DAISC, EAISC 0
HDB3/ B3ZS Decoder
Line Loopback
CVs
0
Counter
Errors PRBS Analyzer 1 ENANA
DS3/E3 AIS GEN
L3LBK & LLBAIS FLBK
RAISGN RPBRS 1 0 1 2
RX PRBS GEN
1 0
From Desynchronizer
CLK* DAISC, EAISC
0 0 1 DAISC, EAISC
HDB3/ B3ZS Coder DS3/E3 AIS GEN
RX
3
*Note: The Tx and Rx PBRS Generators will normally use their respective clocks for pattern generation. If the normal clock is missing, the AIS clock appropriate to the application will be used to generate the pattern.
Rx Output
FLBK 0 0 1 1 L3LBK & LLBAIS 0 1 0 1 Rx Output Rx Data DS3/E3 AIS Tx Data Rx Data
- 59 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
BOUNDARY SCAN Introduction The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. As shown in Figure 37, one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). The boundary scan capability is based on a Test Access Port (TAP) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. The boundary scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) and Test Reset (TRS)) and a Test Data Output (TDO) output signal. Boundary scan signal timing is shown in Figure 26. The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. The TAP controller is reset by asserting the TRS lead low for a minimum of 250 nanoseconds. Detailed information on the operation of this state machine can be found in the IEEE 1149.1 standard. The serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. These three serial registers are connected in parallel between the Test Data Input (TDI) and Test Data Output (TDO) signals, as shown in Figure 37. The boundary scan function will be reset and disabled by holding lead TRS low. When boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the TL3M device's internal logic. During boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. Boundary Scan Operation The maximum frequency the TL3M device will support for boundary scan is 10 MHz. The timing diagrams for the boundary scan interface leads are shown in Figure 26. The instruction register contains three bits. The TL3M device performs the following six boundary scan test instructions: The EXTEST test instruction (000) provides the ability to test the connectivity of the TL3M device to external circuitry. The SAMPLE test instruction (001) provides the ability to examine the boundary scan register contents without interfering with device operation. The BYPASS test instruction (111) provides the ability to bypass the TL3M boundary scan and instruction registers. The IDCODE test instruction (110) activates output on lead TDO of the device ID information. The MEMBIST test instruction (101) provides a means of testing all internal RAMs. This function is intended for TranSwitch manufacturing test only. The HI-Z test instruction (011) places all outputs in a high impedance state. During the Capture - IR state, a fixed value (101) is loaded into the instruction register. Boundary Scan Chain There are 163 scan cells in the TL3M boundary scan chain. Bidirectional signals require two scan cells. Additional scan cells are used for direction control as needed. A Boundary Scan Description Language (BSDL) source file is available via the Products page of the TranSwitch World Wide Web site (www.transwitch.com).
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 60 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Figure 37. Boundary Scan Schematic
Boundary Scan Register
CORE LOGIC OF TL3M DEVICE
Signal input and output leads (solder balls on bottom surface of PBGA package)
MEMBIST Register ID Register Instruction Register Bypass Register TAP Controller
TDI
3 Clock, Controls TCK, TMS, TRS IN OUT Boundary Scan Serial Test Data
TDO
- 61 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
MEMORY MAP
There are four memory map segments. One, with leading address digit 0, contains registers used for global (common) operation, including device identification (ID). The other three segments have addresses with leading digit X, and their registers correspond to the mapper channel identified by X (where X = 1, 2, 3). Register status types are: R/W: Read/write; R: Read only; R(L)/W: Read(Latched)/Write. Read only registers must not be written. Registers that are shown with all bits Reserved must not be accessed, unless otherwise indicated. When writing to a register that contains from one to seven bits that are shown as Reserved or Not Used, these bits should be written as zeros, unless otherwise indicated. Please note that Reserved bits may perform specific test functions and must be set to the specified value when written in order to assure proper device operation, while Not Used bits have no function but should to be set to the specified value when written in case they are assigned functions in future versions of the device, for purposes of backwards compatibility with existing application designs. Please note that a hardware reset (lead RESET), or a software reset via control bit RESETS (bit 0 in register 0C7H), will result in all per channel control bits, Reserved and Not Used bits in used registers (1CXH-3CXH, where X = any listed value in the memory map) being reset to the 1 state, and all common control bits, Reserved and Not Used bits in used registers (0CXH) being reset to the 0 state. DEVICE IDENTIFICATION REGISTERS (Manufacturer ID plus Triple Level 3 Mapper ID)) Address Status (Hex)
0F0 0F1 0F2 0F3 0F4 R R R R R
Bit 7
1 1 1 0
Bit 6
1 1 1 0
Bit 5
0 0 0 1
Bit 4
1 1 1 1
Bit 3
0 0 0 0
Bit 2
1 0 1 0
Bit 1
1 0 1 0
Bit 0
1 0 1 0
Set to 0
Set to 0
Description The manufacturer and device identifiers are based on the manufacturer ID format given in IEEE standard 1149.1 on Boundary Scan, the ID number assigned by the Solid State Products Engineering Council (JEDEC) to The TranSwitch Corporation, and the part number digits assigned to the TL3M device by TranSwitch. The serial format for this 4-byte ID is shown below, where the MSB is bit 7 in register 0F3H and the LSB (fixed at the value of 1) is bit 0 in register 0F0H: MSB Revision 4-bits Part Number 16 bits Manufacturer Identify 11 bits LSB 1
The manufacturer ID for all TranSwitch devices is defined as the binary equivalent of 107, located in bits 3 through 0 in register 0F1H, and bits 7 through 1 of register 0F0H. The part number of the TL3M is 03453, which is expressed as a binary number in bits 3 through 0 in register 0F3H, bits 7 through 0 in register 0F2H, and bits 7 through 4 in register 0F1H. The revision field is in bits 7 through 4 of register 0F3H.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 62 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
CORE IDENTIFICATION REGISTERS (Manufacturer ID plus Level 3 Mapper Core ID) Address XF0 XF1 XF2 XF3 XF4 Description A core ID is provided in registers XF0H through XF4H for each of the L3M mapper channel cores. A core ID is indicated by the value of 90 hex in the XF4H register. The core ID is otherwise similar in format to the device ID in registers 0F0H through 0F3H, except that the part number and revision fields correspond to the basic L3M mapper core, part number 03452. COMMON CONTROL REGISTERS Address Status (Hex)
0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 R/W Reserved R/W Reserved Reserved RESET3 RESET2 RESET1 RESETS R/W Reserved
Status R R R R R
Bit 7 1 1 1 0 1
Bit 6 1 1 1 0 0
Bit 5 0 0 0 1 0
Bit 4 1 0 1 1 1
Bit 3 0 0 0 0 0
Bit 2 1 0 1 0 0
Bit 1 1 0 1 0 0
Bit 0 1 0 1 0 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved Reserved INTZN Reserved Reserved TSTCH1 TSTCH0 LLBAIS INTEN ADDEN L3EN
PER CHANNEL CONTROL REGISTERS Where X=1, 2, or 3, which corresponds to the selected channel: Address (Hex)
XC0 XC1 XC2 XC3 XC4 XC5 XC6 XC7 XC8 XC9 XCA
Mode*
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
BFOM1 DECODE ALM2AIS EXN1 EXOO COR TESTB3
Bit 6
BFOM0 CODE Reserved EXK3 Reserved Reserved FIXPTR
Bit 5
DPOS1 INVCI TLAISGN EXF3 RAMRDI
Bit 4
DPOS0 INVCO TPAISGN EXH4 REIEN POH2RAM PAT23 Reserved
Bit 3
APOS1 RING TPAIS00 EXF2 RAISGN ENANA
Bit 2
APOS0 FLBK Reserved EXG1 RAISEN TXANA TXRST
Bit 1
Reserved L3LBK ADBEN EXC2 WGDEC TPRBS RXRST RDI5
Bit 0
DS3 Reserved L3OEN EXJ1 PSL2AIS RPRBS RESETC REIBLK
XALM2AIS Reserved TLOC2AIS TLOS2AIS
Reserved
C2 Compare Reserved Reserved NOPOH Reserved
- 63 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
COMMON STATUS REGISTERS Address (Hex)
0B0 0B1 0B2-0B5 0B6 0B7 R ADBCN ADBCN
Mode
R
Bit 7
Bit 6
Bit 5
Reserved Reserved
Bit 4
Bit 3
Bit 2
INT3 INT3
Bit 1
INT2 INT2
Bit 0
INT1 INT1
R(L)/W
Not Used Reserved Reserved
R(L)/W
DEVICE COMMON INTERRUPT MASK OR ENABLE REGISTERS Address (Hex)
0BA 0BB 0BC 0BD R/W ADBCN
Mode
R/W
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
INT3
Bit 1
INT2
Bit 0
INT1
Not Used Not Used Reserved
PER CHANNEL STATUS REGISTERS Where X=1, 2, or 3, which corresponds to the selected channel: Address (Hex)
XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7
Mode
R
Bit 7
DLOC DLOC RDI RDI SINT
Bit 6
DLOJ1 DLOJ1 L3LOS L3LOS Reserved Reserved LOVFL LOVFL
Bit 5
BUSERR BUSERR L3LOC L3LOC J1NEW J1NEW RFRST RFRST
Bit 4
E1AIS E1AIS TOVFL TOVFL TUG3NEW TUG3NEW TFRST TFRST
Bit 3
LOP LOP L3AIS L3AIS ROVFL ROVFL PLLLOC PLLLOC
Bit 2
PAIS PAIS RAMLOC RAMLOC AISLOC AISLOC TPLOC TPLOC
Bit 1
PSLERR PSLERR ALOC ALOC XISTAT XISTAT RPLOC RPLOC
Bit 0
C2EQ0 C2EQ0 ALOJ1 ALOJ1 XPAIS XPAIS OOL OOL
R(L)/W
R
R(L)/W
R
R(L)/W Reserved
R L3ERR L3ERR
R(L)/W
PER CHANNEL INTERRUPT MASK OR ENABLE REGISTERS Where X=1, 2, or 3, which corresponds to the selected channel: Address (Hex)
XBA XBB XBC XBD
Mode
R/W R/W R/W R/W
Bit 7
DLOC RDI HINT L3ERR
Bit 6
DLOJ1 L3LOS Reserved LOVFL
Bit 5
BUSERR L3LOC NEW RFRST
Bit 4
E1AIS TOVFL TUG3NEW TFRST
Bit 3
LOP L3AIS ROVFL PLLLOC
Bit 2
PAIS RAMLOC AISLOC TPLOC
Bit 1
PSLERR ALOC XISTAT RPLOC
Bit 0
C2EQ0 ALOJ1 XPAIS OOL
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 64 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
PER CHANNEL TRANSMIT POH BYTE AND O-BIT REGISTERS Where X=1, 2, or 3, which corresponds to the selected channel: Address Status (Hex)
X00 to X3F X40 X41 X42 X43 X44 X45 X46 X47 X48 X49 R/W Not Used R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit J1 Byte (64 bytes) Transmit B3 Error Mask Transmit C2 Byte Transmit G1 Byte Transmit F2 Byte Transmit H4 Byte Transmit F3 Byte Transmit K3 Byte Transmit N1 Byte Not Used TOBIT2 TOBIT1
PER CHANNEL RECEIVE POH BYTES, TUG-3 H1/H2 BYTES AND O-BIT REGISTERS Where X=1, 2, or 3, which corresponds to the selected channel: Address Status (Hex)
X50 to X8F X90 X91 X92 X93 X94 X95 X96 X97 X98 X99 X9A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive J1 Byte (64 bytes) Receive B3 Byte Receive C2 Byte Receive G1 Byte Receive F2 Byte Receive H4 Byte Receive F3 Byte Receive K3 Byte Receive N1 Byte Receive TUG-3 H1 Byte Receive TUG-3 H2 Byte Not Used ROBIT2 ROBIT1
- 65 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
PER CHANNEL PERFORMANCE COUNTERS AND FIFO LEAK RATE REGISTERS Where X=1, 2, or 3, which corresponds to the selected channel: Address Status (Hex)
XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XAA XAB XAC XAD XAE XAF XFF R R R/W R R R R R R R R R R R R R R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive SDH/SONET Frame Counter (8 bits) Reserved FIFO Leak Rate Register (8 bits) Positive Justification (Increment) Counter (8 bits) Negative Justification (Decrement) Counter (8 bits NDF Counter (8 bits) TUG-3 Positive Justification (Increment) Counter (8 bits) TUG-3 Negative Justification (Decrement) Counter (8 bits) TUG-3 NDF Counter (8 bits) B3 Block Error Counter (8 bits) REI Counter (Low Order Byte) REI Counter (High Order Byte) B3 Parity Error Counter (Low Order Byte) B3 Parity Error Counter (High Order Byte) Coding Violations/PRBS Error Counter (Low Order Byte) Coding Violations/PRBS Error Counter (High Order Byte) Common High Order Byte Counter Snapshot (REI, B3, Coding Violations)
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 66 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
MEMORY MAP BIT DESCRIPTIONS
Please note that all bits in used registers that are shown as Reserved or Not Used should be set to zero when the register is written, unless otherwise indicated. If the register has not been written, or cannot be written, then the values read from such bits may be arbitrary. COMMON CONTROL BIT DESCRIPTIONS Address 0C0 0C1 0C2 Bit 7-0 7-0 7-4 3 INTZN Symbol Reserved Reserved Reserved: Must be set to zero when register is written. Device Interrupt High Impedance (High-Z) Off State Disable: This bit works in conjunction with bit INTEN (bit 2) to control the operation of the interrupt output lead INT/IRQ (lead AB8), as described in the table below. A 1 sets the INT/IRQ lead for normal operation if bit INTEN is 1. The lead will be either high when active with the off state low (Intel mode, INT), or low when active with the off state high (Motorola mode, IRQ). A 0 enables the off state to be high impedance instead, for both modes. INTZN X 0 INTEN 0 1 Interrupt Lead Action Held in the high impedance state Interrupt lead enabled. Held to the high impedance state in the off state, when no interrupts have occurred. Normal operation. Driven to high or low in both active and off states, as defined in the lead description. Description
1
1
2 1
INTEN ADDEN
Device Interrupt Enable: This bit works in conjunction with bit INTZN (bit 3) as described in the table above. Device Add Bus Enable: A 1 enables the following Add bus output signals for a channel if the per channel control bit ADBEN is also a 1: - AD(7-0) data leads - ADD add indication lead - APAR parity lead. A 0 forces these leads to a high impedance state, or to the off state, regardless of the state of ADBEN. A hardware or software reset forces this bit to the 0 state. Device Receive Output and Monitor Signals Enable: A 1 enables the following receive output and monitor signals for a channel if the per channel control bit L3OEN is also a 1: - RCLKn (Receive Clock) - RPOSn (Receive Positive Rail/NRZ) - RNEGn (Receive Negative Rail) - RnNRD (Transmit Monitor NRZ Data) - RnNRC (Transmit Monitor NRZ Clock) A 0 forces these signals to a high impedance state, regardless of the state of L3OEN. A hardware or software reset forces this bit to the 0 state. Reserved Reserved - 67 of 96 -
0
L3EN
0C3 0C4
7-0 7-0
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address 0C5
Bit 7-3 2 1 0
Symbol
Description Reserved: Must be set to zero when register is written.
TSTCH1 TSTCH0 LLBAIS
TranSwitch Test Control Bits: These bits are used for selecting test conditions for each of the three channels. These bits must be set to 00 for normal operation. Line Loopback Receive AIS Output Enable: This bit works in conjunction with the line loopback control bit (L3LBK, Address XC1H, Bit 1) according to the following table. LLBAIS L3LBK Action X 0 Normal channel operation 0 1 Line loopback for channel n; output data is the received data 1 1 Line loopback for channel n; output data is a DS3 or E3 AIS signal. Reserved Reserved: Must be set to zero when register is written. Reset Channel n: When set to 1, these bits are equivalent to applying a hardware reset to each of the three channels. These bits are not self clearing and must be written with a 0 to resume normal operation. Device Reset: When set to 1, this reset bit performs the same functions as the hardware reset lead (RESET). This bit is self clearing and will return to 0 after the reset is complete.
0C6 0C7
7-0 7-4 3 2 1 0 RESET3 RESET2 RESET1 RESETS
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 68 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
PER CHANNEL CONTROL BIT DESCRIPTIONS Note: Registers XC0-XCA are set to FFH in the event of a hardware or software reset. The X in the Register addresses, where X = 1, 2, or 3, corresponds to the selected channel: Address XC0 Bit 7 6 Symbol BFOM1 BFOM0 Description SDH/SONET Bus Operating Format Control Bits: These bits determine the bus operating format according to the table given below: The SDH/ SONET bus operating format control bits must be set to the same value for all three channels. BFOM1 0 0 1 1 XC0 (cont.) 5 4 DPOS1 DPOS0 BFOM0 0 1 0 1 Mapping Format Future Use STS-3 Future Use STM-1 TUG-3
Dropped TUG-3/STS-1 Selection: These bits determine which TUG-3 or STS-1 is to be dropped to the channel from the STM-1 or STS-3 according to the table given below. The same TUG-3 or STS-1 may be dropped to one or more channels depending upon the application. Unused channels should be assigned a TUG-3 and, if desired, the Receive Output Enable bit (Bit 0 of Address XC2H, L3OEN) can be set to 0 (High-Z). DPOS1 0 0 1 1 DPOS0 0 1 0 1 Mapping TUG-3 position A (or STS-1 #1) TUG-3 position B (or STS-1 #2) TUG-3 position C (or STS-1 #3) Do not use
3 2
APOS1 APOS0
Add TUG-3/STS-1 Selection: These bits determine which TUG-3 or STS-1 SPE is to be added from the channel to the STM-1 or STS-3, according to the table given below: Each channel must have a different TUG-3 or STS-1 selection to prevent bus contention. If more than one channel is assigned to the same TUG-3 or STS-1, a common bus contention alarm (ADBCN) will occur. Unused channels should be added to an unassigned TUG-3 position and the Add Bus Enable bit (Bit 1 of Address XC2H, ADBEN) should be set to 0 (High-Z). APOS1 0 0 1 1 APOS0 0 1 0 1 Mapping TUG-3 position A (or STS-1 #1) TUG-3 position B (or STS-1 #2) TUG-3 position C (or STS-1 #3) Do not use
1 0 DS3
Reserved: Must be set to zero when register is written. DS3 Mode: Determines the line to SDH/SONET mapping mode according to the table given below: DS3 0 1 Mapping Mode E3 (34.368 Mbit/s) DS3 (44.736 Mbit/s)
- 69 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XC1
Bit 7
Symbol DECODE
Description Transmit Line Decoder Enabled: A 1 enables the transmit HDB3/ B3ZS decoder (for rail operation). A 0 disables the decoder (for NRZ operation). This control bit also selects the transmit line interface to be either positive/ negative rail (decoder enabled) or NRZ. Receive Line Coder Enabled: A 1 enables the receive HDB3/B3ZS coder (for positive/negative rail operation). A 0 disables the coder (for NRZ operation). This control bit also selects the receive line interface to be either positive/negative rail (coder enabled) or NRZ. Transmit Invert Line Clock Input: When set to 0, the DS3 or E3 line signals for the positive/negative rail or NRZ interface are clocked in on rising edges of the line clock (TCLKn). A 1 enables the line signals to be clocked in on falling edges of the clock. This bit has no effect in facility loopback. Receive Invert Line Clock Output: When set to 0, the DS3 or E3 line signals for the positive/negative rail or NRZ interface are clocked out on falling edges of the clock (RCLKn). A 1 enables the line signals to be clocked out on rising edges of the clock.
6
CODE
5
INVCI
4
INVCO
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 70 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Address XC1 (cont.)
Bit 3
Symbol RING
Description Ring Operating Mode: A 1 enables the alarm indication port REI count and RDI indication to be transmitted in the G1 byte. A 0 enables the local RDI generation or path overhead byte interface to control the transmitted RDI state. The alarm conditions that may cause RDI are shown below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign.
LOP (Alarm) (TUG-3) PAIS (Alarm) (TUG-3) BFOM1=1 DLOJ1 (Alarm) & E1AIS (Alarm) XALM2AIS=0 + ISTAn lead high PAISn lead high XALM2AIS=1 PSLERR (Alarm) C2EQ0 (Alarm) PSL2AIS=1 + & + Send RDI for Channel n
&
+
&
2
FLBK
Facility Loopback: A 1 enables the transmit line data and clock input signals to be looped back internally as the receive line data and clock output signals, as illustrated below. The signals from the Drop bus are disabled.
A SDH/SONET BUS D Channel n TX DS3/E3
RX
1
L3LBK
DS3/E3 Line Loopback: A 1 enables the receive line data and clock output signals to be looped back internally as the transmit line data and clock input signals, as illustrated below. The transmit line input signals are disabled. The receive data and clock are provided at the receive line interface. Please note that when control bit LLBAIS (bit 0 in 0C5H) is a 1, DS3 or E3 AIS is sent downstream instead of the received data.
A SDH/SONET BUS D
TX
Channel n
DS3/E3
RX
DS3/E3 AIS OPTION
0
Reserved: Must be set to zero when register is written.
- 71 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XC2
Bit 7
Symbol ALM2AIS
Description External Alarm Enable AIS: A 1 enables an AIS detected in the SDH/ SONET E1 byte (when control bit XALM2AIS = 0) or a high on either the ISTAn or PAISn leads (when control bit XALM2AIS = 1) to generate DS3 or E3 line AIS in the receive direction when control bit RAISEN is a 1. See logic diagram for Address XC5H, bit 2. Reserved: Must be set to zero when register is written. Transmit Line AIS: A 1 written into this position generates and transmits a DS3 or E3 AIS towards the SDH/SONET Add bus, independent of the state of control bit FLBK (bit 2 in register XC1H). DS3 AIS is defined as a valid Mframe with proper subframe structure. The data payload is a 1010... sequence starting with a 1 after each overhead bit. Overhead bits are as follows: F0=0, F1=1, M0=0, M1=1; C-bits are set to 0; X-bits are set to 1; and P-bits are set for valid parity. E3 AIS is defined as an all ones pattern. Transmit TUG-3 Zeros or Path AIS Enable: A 1 enables TUG-3 unequipped channel generation (SPE with zeros and valid pointer), or a TUG-3 path AIS, towards the SDH/SONET bus, depending on the state of control bit TPAIS00. The logic diagrams for sending TUG-3 path AIS and unequipped are shown below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign.
BFOM1=1 TPAISGN=1 TPAIS00=0 BFOM1=1 TPAISGN=1 TPAIS00=1 & Send TUG-3 Unequipped (zeros) for Channel n & Send TUG-3 Path AIS for Channel n
6 5 TLAISGN
4
TPAISGN
3
TPAIS00
Transmit TUG-3 SPE with Zeros: When enabled by writing a 1 to control bit TPAISGN, a 1 written into this location causes the TUG-3 (POH bytes and payload) to be transmitted with zeros, but with a valid pointer. A 0 causes a TUG-3 path AIS to be transmitted towards the SDH/SONET bus. Reserved: Must be set to zero when register is written. Add Bus Enable: A 0 forces the Add bus data (AD(7-0)) and Add Parity (APAR) leads to a high impedance state, and ADD high. A 1 enables the Add bus for that channel selection. This bit works in conjunction with bit 1 of Address 0C2H, ADDEN. ADDEN ADBEN 0 0 Add bus high-Z 0 1 Add bus high-Z 1 0 Per channel high-Z 1 1 Add bus enabled Please note: This control bit is forced to 0 on a hardware reset or software reset.
2 1 ADBEN
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 72 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Address XC2 (cont.)
Bit 0
Symbol L3OEN
Description Receive Output Enable: A 0 forces the receive interface clock (RCLKn) and data signals (RPOSn and RNEGn), and NRZ outputs (RnNRC and RnNRD) for channel n to a high impedance state. A 1 enables the receive output leads. This bit works in conjunction with bit L3EN (0C2H, bit 0). L3EN L3OEN 0 0 All receive channels high-Z 0 1 All receive channels high-Z 1 0 Per channel high-Z 1 1 Receive outputs enabled Please note: This control bit is forced to 0 on a hardware reset or software reset. Transmit External Interface N1 byte: A 1 enables the N1 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface K3 byte: A 1 enables the K3 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface F3 byte: A 1 enables the F3 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface H4 byte: A 1 enables the H4 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface F2 byte: A 1 enables the F2 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface G1 Byte: A 1 enables the G1 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location or internal logic/alarms to control the transmitted state of REI (FEBE), RDI, and the unassigned bits. Transmit External Interface C2 Byte: A 1 enables the C2 byte from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface J1 Bytes: A 1 enables the J1 bytes from the POH input/output interface to be transmitted. A 0 enables the corresponding RAM segment (64 locations) to be transmitted.
XC3
7
EXN1
6
EXK3
5
EXF3
4
EXH4
3
EXF2
2
EXG1
1
EXC2
0
EXJ1
- 73 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XC4
Bit 7
Symbol EXOO
Description External O-Bit Select: A 1 selects the two Overhead Communication Bits (O-bits) from the external interface (lead TnOCD) as the two O-bits transmitted in each of the nine subframes of the DS3 format or TranSwitch designated reserved bits in each of the three subframes of the E3 format. A 0 enables the two O-bits from the corresponding RAM location to be transmitted (TOBIT2, TOBIT1 at Address X49H). Reserved: Must be set to zero when register is written. Remote Defect Indication Enabled: Enable bit for controlling the generation of Path RDI (bit 5 in G1 byte). When control bits RING and EXG1 are 0, and RAMRDI is a 0, RDI is generated when the following alarms or conditions occur: - Drop bus loss of J1 (DLOJ1) - Drop bus loss of clock (DLOC) - Loss of pointer (LOP) (TUG-3 operation) - Path AIS detected (PAIS) (TUG-3 operation) - Received E1 byte has a majority of 1s and control bit XALM2AIS is 0 - Either the ISTAn or PAISn input lead is high and control bit XALM2AIS is a1 - PSLERR or C2EQ0 alarm, and control bit PSL2AIS is a 1 When control bit RING is a 1, EXG1 is a 0, and RAMRDI is a 0, the RDI state is controlled via the Alarm Indication Port. The microprocessor controls the RDI state when RAMRDI is a 1 and EXG1 is a 0. Note: writing a 1 to the RAMRDI bit will disable the local alarms and the Alarm Indication Port RDI in the ring mode from controlling the state of the transmitted RDI bit. The logic diagram for sending Path RDI is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign.
POH I/O (bit 5 of G1) EXG1=1 RING=0 PSLERR (Alarm) + C2EQ0 (Alarm) PSL2AIS=1 LOP (Alarm) (TUG-3) PAIS (Alarm) (TUG-3) BFOM1=1 DLOJ1 (Alarm) DLOC (Alarm) & E1AIS (Alarm) XALM2AIS=0 ISTAn lead high + PAISn lead high XALM2AIS=1 AIP I/O RDI Value RING=1 RAMRDI=0 RAMRDI=1 & RAM RDI VALUE EXG1=0
6 5 RAMRDI
& & + & + & + & + & +
Send Path RDI for Channel n
& &
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 74 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Address XC4 (cont.)
Bit 4
Symbol REIEN
Description REI Enable: A 1 enables the local B3 parity error count or the remote B3 parity error count to be inserted as the REI value. A 0 written into this position permits the microprocessor to control the value of the REI count. The logic diagram for sending REI for all conditions is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign.
EXG1=1 POH I/O G1 REI Value B3 Error Count & RING=0 AIP REI count & RING=1 REIEN=1 REIEN=0 & RAM REI Value EXG1=0 & + & + & +
SEND REI for Channel n
3
XALM2AIS
External Alarm AIS Lead Enable: A 1 enables the external alarm leads (ISTAn and PAISn) to control alarm generation instead of AIS in the E1 byte. A 0 causes alarm generation to be based on E1AIS from the Drop bus. Reserved: Must be set to zero when register is written. Transmit Loss Of Clock (TLCK) AIS Enable: A 1 enables the channel to send SDH/SONET DS3 AIS or E3 AIS automatically when a transmit line clock failure is detected. The logic diagram for transmitting a line AIS is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign.
L3LOC (Alarm) TLOC2AIS=1 L3LOS (Alarm) TLOS2AIS=1 TLAISGN=1 & & +
SEND DS3 or E3 AIS for Channel n
2 1 TLOC2AIS
0
TLOS2AIS
Transmit Loss Of Signal (TPOSn/TNEGn) AIS Enable: A 1 enables the channel to send DS3 or E3 AIS automatically when a transmit line signal failure is detected, as shown in the logic diagram above. Clear On Read: A 0 enables all performance counters for that channel to become non- saturating with roll over capability. The contents of the counter are not affected by a read cycle. A 1 causes the performance counters to become saturating counters, which clear on a read cycle. Reserved: Must be set to zero when register is written.
XC5
7
COR
6-5
- 75 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XC5 (cont.)
Bit 4
Symbol
Description
POH2RAM Path Overhead Bytes to RAM: This bit works in conjunction with the EXnn control bits that select POH bytes (e.g., EXF2). The following table summarizes the action taken by this bit and an EXnn bit: POH2RAM
1
EXnn (reg. XC3H)
1
Action POH interface byte transmitted and written to RAM location for the selected overhead byte. POH interface byte transmitted for the selected byte; the RAM location holds a microprocessor-written overhead byte value. The POH byte written to RAM by the microprocessor is transmitted.
0
1
X
0
3
RAISGN
Generate Receive Line AIS: A 1 written into this position generates a DS3/E3 AIS towards the line (RPOSn, RNEGn) independent of the state of the receive AIS enable bit (RAISEN). Receive AIS Enable: A 1 enables receive E3 or DS3 Line AIS to be generated when the following alarms/conditions occur: - Loss of Drop bus clock alarm (DLOC) - Loss of Drop bus J1 alarm (DLOJ1) - E1 AIS alarm (E1AIS) and XALM2AIS is 0, and ALM2AIS is a 1 - ISTAn or PAISn lead high and XALM2 is 1, and ALM2AIS is a 1 - Loss of pointer (LOP) (TUG-3) - Path AIS (PAIS) (TUG-3) - PSLERR or C2EQ0 occurs, and Path Signal Label Error Enable AIS control bit (PSL2AIS) is a 1 The logic diagram for generating receive line AIS is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign.
BFOM1=1 LOP (Alarm) (TUG-3) PAIS (Alarm) (TUG-3) +& DLOJ1 (Alarm) DLOC (Alarm) E1AIS (Alarm) & XALM2AIS=0 ISTAn lead high +& + & PAISn lead high XALM2AIS=1 ALM2AIS=1 + PSLERR (Alarm) & C2EQ0 (Alarm) PSL2AIS=1 RAISEN=1 RAISGN=1
2
RAISEN
+
&
+
Send Rx AIS for Channel n
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 76 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Address XC5 (cont.)
Bit 1
Symbol WGDEC
Description Test Equipment BPV Selection: A 1 enables the decoder to detect coding violations as found in `Type 1' test equipment. A 0 enables the decoder to detect coding violations as found in `Type 0' test equipment. The following tables summarize the two decoding procedures for coding violations:
BPV For B3ZS
BPV ++ or -0BV or 000V BB0V after odd B00V after even
"Type 1" Equipment 000 (preceding bit(s) changed) 0000 1000 1000
BPV For HDB3
"Type 0" Equipment 11 011 or 0001 1101 1001
BPV ++ or -0BV or 0000V BB00V after odd B000V after even
"Type 1" Equipment 0000 (preceding bit(s) changed) 00000 10000 10000
"Type 0" Equipment 11 011 or 00001 11001 10001
0
PSL2AIS
Path Signal Label Error Enable AIS: A 1 enables the channel to send DS3 or E3 line AIS automatically towards the receive line, and path RDI when a PSLERR or C2EQ0 alarm occurs. (See RAMRDI and RAISEN for logic diagrams). Reserved: Must be set to zero when register is written. 223-1 Test Pattern Enable: A 0 selects the two PRBS test pattern generators' and the test pattern analyzer's pattern to be 215-1. A 1 selects the pattern generators' and analyzer's pattern to be 223-1. Enable Analyzer: A 1 enables the 215-1 or 223-1 analyzer. PRBS errors are counted in a 16-bit counter in locations XAEH and XAFH. Transmit Analyzer Enable: A 1 connects the analyzer to the transmit NRZ line (DS3/E3) signal after the line decoder. A 0 connects the analyzer to the receive NRZ line data prior to the line coder function. A 1 must be written to control bit ENANA (bit 3) for this bit to function (see Figure 36). Transmit Test Pattern Generator Enable: A 1 enables the transmit test pattern generator and disables the NRZ line decoder output. Receive Test Pattern Generator Enable: A 1 enables the receive test pattern generator and disables the NRZ line coder input from the desynchronizer. Test B3 Byte: A 1 transmits a B3 value written by the microprocessor in location X40H. A 0 enables the test byte to become a test mask. When configured as a test mask, a 1 in one or more bit positions causes those bits in the transmitted B3 byte to be inverted from their calculated values.
XC6
7-5 4 PAT23
3 2
ENANA TXANA
1 0
TPRBS RPRBS
XC7
7
TESTB3
- 77 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XC7 (cont.)
Bit 6
Symbol FIXPTR
Description TUG-3 Fixed Pointer Generation: A 1 forces a fixed pointer of 0 to be generated in the transmitted TUG-3 regardless of any pointer movements (J1 in DC1J1) that may occur on the Drop side when the Drop timing mode is selected, or if a pointer movement (J1 in AC1J1) takes place when Add bus timing is selected. When this bit is written with a 0, a pointer movement on the Add or Drop bus is compensated with an outgoing TUG-3 pointer movement in the opposite direction. Reserved: Must be set to zero when register is written. Transmit Reset: A 1 written into this position resets the transmit section (Line to SDH/SONET) of the channel. This includes the transmit FIFOs and internal counters. The channel's transmitter will remain reset until the microprocessor writes a 0 into this location. Receive Reset: A 1 written into this position resets the receive section (SDH/SONET to Line) of the TL3M device channel. This includes the receive FIFOs and internal counters. The channel's receiver will remain reset until the microprocessor writes a 0 into this location. Reset Performance Counters: A 1 written into this position resets the performance counters to 0 for this channel. This bit is self clearing, and does not require the microprocessor to write a 0 into this location.
5-3 2 TXRST
1
RXRST
0
RESETC
XC8
7-0
C2 Compare Path Signal Label Compare: The bits in this location are compared against the C2 byte received (register X91H) for a signal label mismatch. The relationship between the bits of this microprocessor-written byte and the received C2 byte is shown below: Rx C2 Byte 1 2 6 3 5 4 4 5 3 6 2 7 1 8 0
C2 Compare 7 XC9 7-2 1 RDI5
Reserved: Must be set to zero when register is written. RDI 5 Consecutive Enable: A 1 enables the detection/recovery algorithms of RDI (bit 5 in the G1 byte) to activate on 5 consecutive matches/ mismatches. A 0 enables the detection/recovery of RDI to activate on 10 consecutive matches/mismatches. REI (FEBE) Counter Block Count Enable: A 1 configures the REI (FEBE) counter (register locations XAAH and XABH) to count one or more REI errors per received G1 byte as one error (block). A 0 configures the REI counter to count the number of individual errors detected (1 to 8). Reserved: Must be set to zero when register is written. NOPOH No Path Overhead Bytes: When this bit is set to 1, the VC-4 path overhead time slots of the Add bus data signals AD(7-0) are set to a high impedance and the ADD signal is high during these time slots. When this bit is set to 0 the AD(7-0) byte values are set to 00H and the ADD signal is forced low during the time slots that correspond to the POH bytes. Reserved: Must be set to zero when register is written.
0
REIBLK
XCA
7-6 5
4-0
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 78 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
COMMON STATUS BIT DESCRIPTIONS Status bits report the condition of alarms as both current status (unlatched) and event record (latched) bit positions. The unlatched bit goes to 1 for only as long as the alarm persists, while a latched bit is set to 1 upon the first occurrence of the alarm and it remains active until its register is read, when it is reset to 0. Only latched bits that are read as 1 are reset, to preserve alarms which occur during the read operation. If a current alarm is present after this reset, the corresponding latched bit will be set to 1 again. The unlatched bits occupy even-numbered registers. Their corresponding latched bits are in the same bit positions of the following odd-numbered register. Latched bits activate an interrupt while set to 1, unless their mask bit is set to 0. Address 0B0 Bit 7-3 2 1 0 INT3 INT2 INT1 Symbol Reserved Interrupt Indication (INTn) for Channel n: A 1 indicates that channel n has at least one latched alarm set to 1 that is not masked from causing an interrupt. This bit provides information that enables the microprocessor to read the status bits associated with that channel and determine which alarms have occurred. This register contains latched bits that correspond to the unlatched bits in register 0B0H. These latched bits are reset to 0 when they are read. ADBCN Add Bus Contention Indication: A 1 indicates that more than one channel is attempting to drive the Add bus at the same time. This is usually due to the fact that more than one channel has been assigned to the same TUG-3 or STS-1 in the add direction. Reserved This register contains latched bits that correspond to the unlatched bits in register 0B6H. These latched bits are reset to 0 when they are read. Description
0B1 0B6
7-0 7
6-0 0B7 7-0
PER CHANNEL STATUS BIT DESCRIPTIONS The per channel status bits perform in the same way as described above for common status bits. Where X=1, 2, or 3, which corresponds to the selected channel: Address XB0 Bit 7 Symbol DLOC Description Drop Bus Loss Of Clock Alarm: An unlatched loss of clock alarm occurs when the input Telecom Bus Drop bus clock has been stuck high or low for approximately 225 ns. Recovery occurs within 100 ns of the first bus clock transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function. Drop Bus Loss of J1: An unlatched Drop bus loss of J1 alarm occurs when: - 8 consecutive new J1 positions have been detected or - J1 is stuck low for 8 consecutive frames or - J1 is stuck high for 8 consecutive bytes or - 8 J1 pulses are received in one frame. Recovery occurs when the J1 pulse is detected in the same location for 8 consecutive frames.
6
DLOJ1
- 79 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XB0 (cont.)
Bit 5
Symbol BUSERR
Description Bus Parity Error: This unlatched alarm indicates that a parity error has been detected on the Drop bus. Odd parity is calculated over the DD(7-0), DSPE, DC1J1, and DC1 leads. Other than providing this alarm, no action is taken by the channel or device. E1 Byte AIS Detected: The E1 byte in the VC-4 and the E1 byte plus the adjoining bytes may be used to carry an upstream in-band SDH/SONET line and path AIS indication. This unlatched alarm indicates that AIS has been detected in the E1 byte corresponding to AU-3/STS-3 STS-1. Please note: For TUG-3 operation, the first E1 byte in the VC-4 is monitored. The alarm occurs when 5 out of 8 ones are detected once. Recovery occurs when fewer than 5 out of 8 bits are equal to 1 once. TUG-3 Loss Of Pointer Alarm: An unlatched TUG-3 loss of pointer alarm occurs when a New Data Flag (NDF) or an invalid pointer is detected for eight consecutive frames. Recovery occurs when a valid pointer is received for three consecutive frames. TUG-3 Path AIS Alarm: An unlatched TUG-3 Path Alarm Indication Signal (PAIS) is activated when all ones are detected in the 16-bit pointer word (H1 and H2) for three consecutive frames. Recovery occurs when a valid NDF is received, or a valid pointer is detected, for three consecutive frames. Path Signal Label Error: This unlatched alarm indicates that the comparison between the received C2 byte and the microprocessor-written C2 byte did not match for 5 consecutive times. Recovery to 0 occurs when the comparison matches five times consecutively. Unequipped Alarm: This unlatched unequipped alarm is detected when the C2 byte is equal to 00H 5 consecutive times. Recovery occurs when the C2 byte is not equal to 00H five consecutive times. This register contains latched bits that correspond to the unlatched bits in register XB0H. These latched bits are reset to 0 when they are read. Receive RDI Alarm: When RDI5 is set to 0, an unlatched RDI alarm occurs when bit 5 in the G1 byte is equal to 1 for 10 consecutive frames. Recovery occurs when a 0 has been detected for 10 consecutive frames. When RDI5 is a 1, detection and recovery of the alarm is set to 5 consecutive events instead of 10. Transmit Line Loss Of Signal: For an E3 signal, an unlatched line loss of signal alarm occurs when either the positive or negative rail is stuck low for 256 bit times. Recovery occurs when there are at least 32 transitions (on both positive and negative rails) in a count of 256 clock cycles. For a DS3 signal, a loss of signal alarm occurs when either the positive or negative rail is stuck low for 200 bit times. Recovery occurs on the first line signal transition (both positive and negative rails). When the interface is configured for NRZ operation, an active high on the TNEGn/LOSn lead can be used to provide an external loss of signal indication. Detection and recovery are immediate, following the LOSn transitions. Transmit Line Loss of Clock: This unlatched alarm indicates the incoming line clock (TCLKn) signal has been stuck high or low for approximately 225 ns. Recovery occurs within 100 ns of the first line clock transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function.
4
E1AIS
3
LOP
2
PAIS
1
PSLERR
0
C2EQ0
XB1 XB2
7-0 7 RDI
6
L3LOS
5
L3LOC
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 80 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Address XB2 (cont.)
Bit 4
Symbol TOVFL
Description
3
2
1
0
XB3 XB4
7-0 7
6 5
4
3
Transmit FIFO Overflow/Underflow: This unlatched alarm indicates that the transmit FIFO has either underflowed or overflowed. The FIFO automatically resets to a preset value on the occurrence of the alarm. Transmit Line E3 AIS Detected: For an E3 signal, this unlatched AIS L3AIS alarm is detected when four or fewer zeros are detected in 1536 bits, twice in a row. Recovery occurs when there are five or more zeros detected in 1536 bits two consecutive times. Please note: DS3 AIS detection is not supported. RAMLOC RAM Loss Of Clock Detected: The RAM clock input (RAMCI) is monitored for a stuck high or low state using the internal PLL clock to activate this unlatched alarm when the input has been stuck for approximately 225 ns. Recovery occurs within 100 ns of the first RAM clock transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function. Add Bus Loss Of Clock: This unlatched alarm is enabled when the Add bus ALOC timing is selected (lead ABTIM is high). An Add bus loss of clock alarm occurs when the input add clock (ACLK) is stuck high or low for approximately 225 ns. Recovery occurs within 100 ns of the first bus clock transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function. Add Bus Loss of J1: This unlatched alarm is enabled when the Add bus ALOJ1 timing is selected (lead ABTIM is high). An Add bus loss of J1 alarm occurs when: - 8 consecutive new J1 positions have been detected or - J1 is stuck low for 8 consecutive frames or - J1 is stuck high for 8 consecutive bytes or - 8 J1 pulses are received in one frame. Recovery occurs when the J1 pulse is detected in the same location for 8 consecutive frames. This register contains latched bits that correspond to the unlatched bits in register XB2H. These latched bits are reset to 0 when they are read. Software Interrupt: This unlatched software interrupt indication occurs SINT when one or more bit locations in the interrupt mask locations has been set to 1, and a corresponding latched alarm becomes active. The SINT state is exited when the last latched alarm causing the interrupt is cleared (i.e., when its register is read) or the corresponding bit in the interrupt mask is turned off. Reserved J1 New Alarm: An unlatched indication that a new J1 location, other than J1NEW those resulting from pointer movements, has been detected in the VC-4 or STS-3 STS-1. TUG3NEW TUG-3 New Alarm: An unlatched TUG-3 new indication occurs when three consecutive new pointers, or an NDF and a match of the SS bits while the pointer offset value is in range, have been detected. Receive FIFO Overflow/Underflow: This unlatched alarm indicates the ROVFL pointer leak FIFO has underflowed or overflowed. When this occurs, the FIFO will automatically reset to a preset position and the FIFO Reset Indication output lead (DFnE) will pulse high.
- 81 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XB4 (cont.)
Bit 2
Symbol AISLOC
Description AIS Loss Of Clock Detected: The AIS selected (DS3 or E3) is monitored for a stuck high or stuck low condition, An unlatched AIS LOC indication occurs when the EAIS or DAIS clock is stuck high or low for approximately 225 ns. Recovery occurs within 100 ns of the first EAIS or DAIS clock cycle transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function. External STS-1 Alarm: This unlatched alarm indicates that the input on the lead labeled ISTAn is high. It may be used to indicate an external alarm condition (e.g., LOP). Detection and recovery follow ISTAn immediately. External Path AIS: This unlatched alarm indicates that the input on the lead labeled PAISn is high. It may be used to indicate an external alarm condition (e.g., path AIS). Detection and recovery follow PAISn immediately. Reserved: Must be set to zero when register is written. Reserved: This register contains latched bits that correspond to the unlatched bits 5-0 in register XB4H. These latched bits are reset to 0 when they are read. Analyzer Error Indication: This unlatched alarm indicates that the 215-1 or 223-1 PRBS test analyzer has detected an error when enabled. A 1 written to ENANA (bit 3, in XC6H) enables the analyzer. When control bit ENANA is a 0, the analyzer and alarm are disabled. Receive Leak FIFO Overflow/Underflow Alarm: This unlatched alarm indicates that the receive FIFO has either underflowed or overflowed. The FIFO automatically resets to a preset value on the occurrence of the alarm. Receive FIFO Reset Indication: This unlatched alarm indicates that either the leak FIFO or the receive dejitter FIFO has been reset. This may occur because of a FIFO overflow/underflow alarm, or when the receive section has been reset by writing a 1 to control bit RXRST, or upon hardware reset. Transmit FIFO Reset Indication: This unlatched alarm indicates that the transmit FIFO has been reset. This may occur because of a FIFO overflow/ underflow alarm, or when the transmitter has been reset by writing a 1 to control bit TXRST, or upon hardware or software reset. Desynchronizer Phase Lock Loop Loss Of Clock: This unlatched alarm indicates the internal PLL has experienced loss of clock for approximately 225 ns. Recovery occurs within 100 ns of the first PLL clock transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function. Loss of Transmit PLL Clock: This unlatched alarm indicates that the internal transmit PLL clock has been stuck high or low for approximately 250 ns. Recovery occurs within 100 ns of the first PLL clock transition. DCLK (lead K3) must be present for this alarm to function. Loss of Receive PLL Clock: This unlatched alarm indicates that the internal receive PLL clock has been stuck high or low for approximately 225 ns. Recovery occurs within 100 ns of the first PLL clock transition. ACLK (lead P1), when ABTIM (lead B21) is asserted or DCLK (lead K3), when ABTIM is unasserted, must be present for this alarm to function. Analyzer Out of Lock: This unlatched alarm indicates that the PRBS test analyzer, when enabled, is out of lock. This register contains latched bits that correspond to the unlatched bits in register XB6H. These latched bits are reset to 0 when they are read.
1
XISTAT
0
XPAIS
XB5
7 6 5-0 7 L3ERR
XB6
6
LOVFL
5
RFRST
4
TFRST
3
PLLLOC
2
TPLOC
1
RPLOC
0 XB7 7-0
OOL
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 82 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
COMMON INTERRUPT MASK BIT DESCRIPTIONS A 1 written to any of the bits in these common interrupt mask registers, and a 1 state for the corresponding latched alarm bit of the same channel in registers 0B1H and 0B7H, causes a hardware interrupt to occur on the INT/IRQ output lead if control bit INTEN (bit 2 in register 0C2H) is set to 1. Address 0BA Bit 7-3 2 1 0 0BD 7 INT3 INT2 INT1 ADBCN Symbol Reserved Mask for Interrupt Indication for Channel n: A 1 written to a bit enables the corresponding latched status alarm INTn in register 0B1H to cause a hardware interrupt. Mask for Add Bus Contention: A 1 written to this location enables the corresponding status alarm ADBCN in register 0B7H to cause a hardware interrupt. Reserved Description
6-0
PER CHANNEL INTERRUPT MASK BIT DESCRIPTIONS A 1 written to any of the bits in these per channel interrupt mask registers (except HINT), and a 1 state for the corresponding latched alarm bit of the same channel in registers XB1H, XB3H, XB5H (Bits 5-0), and XB7H, causes a software interrupt (SINT) to occur for the channel. If the hardware interrupt bit (HINT) is also written with a 1, and if control bit INTEN (bit 2 in 0C2H) is set to 1, a hardware interrupt will also occur on the INT/IRQ output lead. Where X=1, 2, or 3, which corresponds to the selected channel: Address XBA Bit 7 6 5 4 3 2 1 0 XBB 7 6 5 4 3 2 1 0 Symbol DLOC DLOJ1 BUSERR E1AIS LOP PAIS PSLERR C2EQ0 RDI L3LOS L3LOC TOVFL L3AIS RAMLOC ALOC ALOJ1 Drop Bus Loss Of Clock Drop Bus Loss of J1 Bus Parity Error E1 Byte AIS detected Loss Of Pointer (TUG-3 operation) Path AIS (TUG-3 operation) Path Signal Label Error C2 Equal to 0 alarm (unequipped) Receive RDI (yellow) detected. Transmit Line Loss Of Signal Transmit Line Loss Of Clock Transmit FIFO Error (underflowed or overflowed) E3 Transmit Line AIS Detected RAM Loss Of Clock Add Bus Loss Of Clock Add Bus Loss of J1 Description
- 83 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address XBC
Bit 7 6 5 4 3 2 1 0
Symbol HINT NEW ROVFL AISLOC XISTAT XPAIS L3ERR LOVFL RFRST TFRST PLLLOC TPLOC RPLOC OOL Hardware Interrupt Enable
Description
Reserved: Must be set to zero when register is written. New Alarm - NDF and 3x new pointer events (TUG-3 operation) Receive FIFO Overflow/Underflow Alarm Indication Signal Loss Of Clock External STS-1 Alarm (ISTAn) signal detected as a 1 (if enabled) External Path AIS (PAISn) signal detected as a 1 (if enabled) Internal PRBS Test Analyzer bit error detected. Leak FIFO Overflow/Underflow Receive FIFO Reset Indication Transmit FIFO Reset Indication Desynchronizer Phase Lock Loop (PLL) Loss Of Clock Transmit PLL loss of clock Receive PLL loss of clock PRBS Test Analyzer out of lock. TUG3NEW TUG-3 New Alarm - Three new pointer events
XBD
7 6 5 4 3 2 1 0
PER CHANNEL TRANSMIT PATH OVERHEAD BYTES AND O-BIT DESCRIPTIONS The nine Transmit Path Overhead bytes consist of the J1, B3, C2, G1, F2, H4, F3, K3, and N1 bytes. The POH bytes may be individually transmitted from the POH interface, or from RAM locations written by the microprocessor. When control bit POH2RAM is a 1, the POH interface byte selected for transmission is written into the designated RAM location. For example, if EXC2 is set to 1, the transmit POH interface C2 byte is written into the assigned RAM location, in addition to being transmitted. If EXC2 is set to 0, the transmitted byte is the value written into the corresponding RAM location by the microprocessor. When a 0 is written into the POH2RAM control bit, the capability of writing any of the selected POH interface bytes into their RAM locations is disabled. However, individual bytes may still be transmitted from either the POH interface or the microprocessor-written RAM location. This feature permits switching back and forth between a selected POH interface byte or a RAM location for transmission, without having to re-initialize the RAM location. The following table is a summary of this operation: POH2RAM XC5H, bit 4 1 0 X
* e.g., nn = C2.
EXnn* XC3H, bits 7-0 1 1 0
Action for associated POH byte POH interface byte written into RAM, and also transmitted. POH interface byte transmitted, but not written into RAM. Microprocessor writes RAM value as required. POH RAM value transmitted.
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 84 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
The relationship between a transmitted path overhead byte and the corresponding RAM location is as follows: Bits in a RAM Location 7 6 5 4 3 2 1 0
Bits of Transmitted POH Byte 1 2 3 4 5 6 7 8
For example, if a 01 hex (0000 0001) is written into a RAM location, a 01 hex (0000 0001), starting with bit 1 (a 0), is transmitted. The O-bits consist of two overhead communication bits per subframe, for nine subframes, in the DS3 format, or for 3 designated subframes in the E3 format. Please note that the ETSI and ITU standards do not specify an overhead channel in the E3 mapping format. The selection of the two bits per subframe, either from the O-bit interface or from RAM, operates in the same way as the path overhead bytes, but the O-bits from the transmit O-bit port are not written into the designated RAM location. Where X=1, 2, or 3, which corresponds to the selected channel:
Address X00 to X3F X40
Bit 7-0
Symbol J1
Description Transmit Path Trace: The bytes written into these 64 registers provide a repetitive 64-byte fixed length message for transmission. The bytes written into these positions are either from the microprocessor or from the external POH input/output interface. The starting address is arbitrary. Transmit B3 Error Mask: When control bit TESTB3 (bit 7 in XC7H) is a 0, the bits in this register that are written with a one represent the columns in the B3 byte in which errors will be generated. The error is created by inverting the calculated B3 bit position. For example, if a 01 hex is written into this register. Bit 8 in the B3 byte will be transmitted inverted. The B3 errors are sent until this register is rewritten with a 00H. When control bit TESTB3 is a 1, the value written into this register location is the transmitted B3 byte.
7-0
B3 Error Mask
X41
7-0
C2
Transmit Path Signal Label (microprocessor-written value): The bits of the C2 byte that are written into this position indicate the construction of the AU-3, TUG-3, or SPE (e.g., unequipped).
- 85 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
Address X42
Bit 7-0
Symbol G1
Description Transmit G1 Byte: This byte is used for sending the microprocessor-controlled states for REI, RDI, and any unassigned bits, according to the states given in the tables below: TFEBE EXG1 0 0 1 REIEN 0 1 X Action Microprocessor-written value sent Internal or mate (ring mode) value sent External POH I/O interface value sent TRDI EXG1 0 0 1 RAMRDI 0 1 X Action Internal or mate (ring mode) value sent Microprocessor-written value sent External POH I/O interface value sent Unassigned Bits EXG1 0 1 Action Microprocessor-written value sent External POH I/O interface value sent
X43
7-0
F2
Transmit F2 (User) Channel: This location contains either a microprocessor-written value or a POH input/output interface value prior to transmission. Transmit H4 Byte: This location contains either a microprocessor-written value or a POH input/output interface value prior to transmission. This byte is not used for E3 or DS-3 to SDH/SONET applications and is normally sent with a value equal to 00H. Transmit F3, K3, and N1 Bytes: These locations contain either a microprocessor-written value or a POH input/output interface value prior to transmission. Not Used Not Used Transmit O-Bits: These two bits correspond to the two O-bits found in each of the nine subframes in the DS3 format or the TranSwitch designated reserved bits in the three subframes in the E3 format. The O-bits are read once per frame and inserted into each of the subframes.
X44
7-0
H4
X45 X46 X47 X48 X49
7-0 7-0 7-0 7-0 7-2 1 0
F3 K3 N1
TOBIT2 TOBIT1
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 86 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
PER CHANNEL RECEIVE PATH OVERHEAD BYTES, TUG-3 H1/H2 BYTES AND O-BIT DESCRIPTIONS The selected TUG-3 or STS-3 STS-1 received path overhead bytes are written into the locations given below, and are also provided at the receive path overhead byte interface for use by external circuitry, as required. The relationship between a received path overhead byte and the corresponding RAM location is as follows: Bits of RAM Location: 7 6 5 4 3 2 1 0
Bits of Received POH Byte: 1 2 3 4 5 6 7 8
Where X=1, 2, or 3, which corresponds to the selected channel: Address X50 to X8F X90 X91 X92 Bit 7-0 7-0 7-0 7-0 Symbol J1 B3 C2 G1 Description Receive Path Trace: The received J1 bytes are written into this 64-byte segment in a rotating fashion. There is no specific starting point. Receive Path B3 Byte: This register provides the received B3 parity byte. Receive Path Signal Label: These bits indicate the construction of the AU-3, TUG-3, or SPE (e.g., unequipped). Receive G1 Byte: This location provides the receive status of the REI bits (bits 7-4), Path RDI (bit 3), and any unassigned bits in the G1 byte (bits 2-0). RAM Bit Receive G1 Bit X93 X94 X95 X96 X97 X98 X99 7-0 7-0 7-0 7-0 7-0 7-0 7-0 F2 H4 F3 K3 N1 H1 H2 7 1 6 2 5 3 4 4 3 5 2 6 1 7 0 8
Receive F2 (User) Channel: This register provides the F2 path overhead byte. Receive H4 Byte: This byte is not specified for use in this application. It is provided for future use as required. Other Receive Path Overhead Bytes: These registers provide access to the F3, K3, and N1 bytes, as required. Received TUG-3 H1 and H2 Pointer Bytes: The contents of the H1 and H2 pointer bytes for a TUG-3 are provided in the following bit order for microprocessor read access. H1 (X98H) H2 (X99H) Bit 7 6 5 4 3 2 1 0 76543210 NNNNSS ID I DI DI DI D Not Used Receive O-Bits: The received states of the two Overhead Communication channel bits found in the nine subframes in the DS3 format or the three TranSwitch-designated subframes in the E3 format. The two bits are updated once a frame from one of the subframes in the frame.
X9A
7-2 1 0 ROBIT2 ROBIT1
- 87 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
PER CHANNEL PERFORMANCE COUNTERS AND FIFO LEAK RATE REGISTER DESCRIPTIONS Some performance counters have 8 bits and some have 16 bits. All 16-bit performance counters allow uninterrupted access, without the danger of one byte changing while the other byte is read. To perform a 16-bit read, the low order byte is read first. This causes a snapshot of the simultaneous value of the high order byte of the counter to be transferred to a common high order byte at location FFH. The common high order byte should be read next to complete the count transfer. If another performance counter low order byte is read first, the contents of the common high order byte will change to reflect the high order byte of the performance counter just read. Counts that occur during the read cycle are held for the counter to be updated afterwards. All the performance counters can also be configured to be either saturating or non-saturating. When a 1 is written to control bit COR (clear on read), the performance counters are configured to be saturating, with the counters stopping at their maximum count. An 8-bit or 16-bit saturating counter is reset on a microprocessor read cycle. When a 0 is written to control bit COR, the performance counters are configured to be non-saturating, and roll over to zero after the maximum count in the counter is reached. The counters are not cleared on a read cycle. All the performance counters can be reset simultaneously by writing a 1 to control bit RESETC. This bit is self clearing, and does not require writing a 0 into this location. See exceptions for XA0H and XA2H below. All drop-bus related performance counters are inhibited (i.e., will not increment) when one or more of the following alarms occurs: - Loss of Drop bus clock alarm (DLOC) - Loss of Drop bus J1 alarm (DLOJ1) - AIS detected in the E1 byte (when XALM2AIS = 0) - When either ISTAn or PAISn lead is high (when XALM2AIS = 1) - Loss of pointer alarm (TUG-3) - Path AIS alarm (TUG-3) The performance counters can also be written by the microprocessor. However, when writing to a 16-bit counter (at locations n, n+1) it is recommended that the low order byte at location n should be written first. The high order byte can then be written by addressing location n + 1. Since the writes occur in separate cycles, care must be taken to prevent the low byte from passing FFH and incrementing the high byte before the high byte is initialized. Writing a low byte equal to 00H will provide the maximum time for the microprocessor to update the high byte. Where X=1, 2, or 3, which corresponds to the selected channel: Address XA0 Bit 7-0 Symbol Rcv Frame Cnt Description Receive SDH/SONET Frame Counter: Counts the number of received SDH/SONET frames. This register is not cleared by a software reset and must be written to 00H to be cleared. Reserved FIFO Leak Rate FIFO Leak Rate Register: When a value greater then 00H is written into this location, this number represents the number of frames between consecutive leaked bits, in multiples of four frames (i.e., a value of x means that there are 4x frames between bit leaks). The value of zero enables an internal TranSwitch pointer leak algorithm. The algorithm is TranSwitch proprietary. This register is not cleared by a software reset and must be written to 00H to be cleared.
XA1 XA2
7-0 7-0
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 88 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
Address XA3
Bit 7-0
Symbol INC Count
Description Positive Justification (Increment) Counter: Counts the number of positive (increment) pointer movements in the AUG/VC-4 or STS-3/STS-1 based on incoming J1 movements in the C1J1 signal.
XA4
7-0
DEC Count Negative Justification (Decrement) Counter: Counts the number of negative (decrement) pointer movements in the AUG/VC-4 or STS-3/STS-1 based on the incoming J1 movements in the C1J1 signal. NDF Count New Data Flag (NDF) Counter: Counts the number of the incoming J1 movements for the AUG/VC-4 or STS-3/STS-1 in the C1J1 signal. TUG-3 INC Count TUG-3 Positive Justification (Increment) Counter: Counts the number of positive (increment) pointer movements in the TUG-3, based on interpretation of H1 and H2.
XA5 XA6
7-0 7-0
XA7
7-0
TUG-3 Negative Justification (Decrement) Counter: Counts the number TUG-3 DEC Count of negative (decrement) pointer movements in the TUG-3, based on interpretation of H1 and H2. TUG-3 NDF TUG-3 New Data Flag (NDF) Counter: Counts the number of New Data Flags (NDFs) or new pointers in the TUG-3 pointer (H1/H2). Count B3 Block Count B3 Block Error Counter: Counts the number of B3 blocks which are received in error. One or more B3 errors per frame is equal to one block error.
XA8 XA9
7-0 7-0
XAA, XAB
7-0
REI Counter Remote Error Indication (REI) Error Counter: Counts the REI error count indication received in bits 1 through 4 of the G1 byte when control bit REIBLK is a 0. When control bit REIBLK is a 1, one or more REI errors are counted as one block error. Register location XAAH is defined as the low order byte, while register location XABH is the high order byte of the 16-bit counter. After reading the low order byte from register location XAAH the stored simultaneous value of the corresponding high order byte (XABH) should be read from XFFH. B3 Counter B3 Parity Error Counter: Counts the number of B3 errors between the incoming received B3 byte and the calculated value. Register location XACH is defined as the low order byte, while register location XADH is the high order byte of the 16-bit counter. After reading the low order byte from register location XACH, the stored simultaneous value of the corresponding high order byte (XADH) should be read from XFFH. CV/PRBS HDB3/B3ZS Coding Violations/PRBS Error Counter: Counts the numError Counter ber of internal coding violation errors detected when the positive/negative rail interface is selected. Register location XAEH is defined as the low order byte while register location XAFH is the high order byte of the 16-bit counter. When control bit ENANA is set to 1, PRBS errors are counted instead when the internal PRBS test analyzer is in lock (i.e., no OOL alarm). After reading the low order byte from XAEH the stored simultaneous value of the corresponding high order byte (XAFH) should be read from XFFH. Common High Byte Snapshot Common High Order Byte Counter Snapshot: This location contains a copy of the high order byte value that existed when the low order byte of a 16-bit counter was last read (i.e., registers XABH, XADH, or XAFH).
XAC, XAD
7-0
XAE, XAF
7-0
XFF
7-0
- 89 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
PACKAGE INFORMATION
The TL3M device is packaged in a 324-lead plastic ball grid array package suitable for surface mounting, as illustrated in Figure 38.
E E2
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AB Y W V U T R P N M L K J H G F E D C B A AA
Bottom View -E1-
TRANSWITCH
TXC-03453BIOG
D D2 E1/4 Note 2
-D1-
D1/4
(A3)
A2
A A1
e
b
Dimension (Note 1) Notes: 1. All dimensions are in millimeters. Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90 angle, or chamfered for A1 identification. 3. Size of array: 22 x 22, JEDEC code MO-151-AAJ-1. A A1 A2 A3 (Ref.) b (Ref.) D D1 (BSC) D2 E E1 (BSC) E2 e (BSC)
Min 2.02 0.40 1.12 0.50 0.63 23.00 21.00 19.45 23.00 21.00 19.45 1.00
Max 2.44 0.60 1.22 0.62
20.20
20.20
Figure 38. TL3M TXC-03453B Package Diagram
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 90 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
ORDERING INFORMATION
Part Number: TXC-03453BIOG 324-lead plastic ball grid array package
RELATED PRODUCTS
TXC-02030, DART VLSI Device (Advanced E3/DS3 Receiver/Transmitter). DART performs the transmit and receive line interface functions required for transmission of E3 (34.368 Mbit/s) and DS3 (44.736 Mbit/s) signals across a coaxial interface. TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock and Data Output). Transmits and receives at STS-3/STM-1 rates. Provides the complete STS-3/STM-1 frame synchronization function. Connects directly to optical fiber interface components. TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). This device performs section, line and path overhead processing for STS-1 SONET signals. Has programmable STS-1 or STS-N modes. TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line and path overhead processing for STM-1/STS-3/STS-3c signals. Compliant with ANSI and ITU-TSS standards. TXC-03303, M13E VLSI Device. Single-chip with extended features multiplex/demultiplex device provides the complete interfacing function between a single DS3 signal and 28 independent DS1 signals. TXC-03305, M13X VLSI Device (DS3/DS1 Mux/Demux). This single-chip device provides the functions needed to multiplex and demultiplex 28 independent DS1 signals to and from a DS3 signal with either an M13 or C-bit frame format. It includes some enhanced features relative to the M13E device. TXC-03452B, L3M VLSI Device (Level 3 Mapper). Maps a 44.736 Mbit/s DS3 or 34.368 Mbit/s E3 asynchronous line signal into an STM-1/STS-3/STS-1 formatted synchronous signal. Separate Add/Drop bus timing is available for loop multiplexers. The L3M provides the overhead processing for the mapped signal. TXC-06103, PHAST-3N VLSI Device (SDH/SONET STM-1, STS-3 or STS-3c Overhead Terminator) This PHAST-3N VLSI device provides a Telecom Bus interface for downstream devices and operates from a power supply of 3.3 volts. TXC-06125, XBERT VLSI Device (Bit Error Rate Generator Receiver). Programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability.
- 91 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
STANDARDS DOCUMENTATION SOURCES
Telecommunication technical standards and reference documentation may be obtained from the following organizations:
ANSI (U.S.A.):
American National Standards Institute 25 West 43rd Street New York, New York 10036 Tel: (212) 642-4900 Fax: (212) 398-0023 Web: www.ansi.org
The ATM Forum (U.S.A., Europe, Asia):
404 Balboa Street San Francisco, CA 94118 ATM Forum Europe Office Kingsland House - 5th Floor 361-373 City Road London EC1 1PQ, England ATM Forum Asia-Pacific Office Hamamatsucho Suzuki Building 3F 1-2-11, Hamamatsucho, Minato-ku Tokyo 105-0013, Japan Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: 20 7837 7882 Fax: 20 7417 7500 Tel: (415) 561-6275 Fax: (415) 561-6120 Web: www.atmforum.com
Bellcore (See Telcordia) CCITT (See ITU-T) EIA (U.S.A.):
Electronic Industries Association Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 Tel: Tel: Fax: Web: (800) 854-7179 (within U.S.A.) (303) 397-7956 (outside U.S.A.) (303) 397-2740 www.global.ihs.com
ETSI (Europe):
European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia-Antipolis Cedex, France Tel: 4 92 94 42 00 Fax: 4 93 65 47 16 Web: www.etsi.org
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 92 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
GO-MVIP (U.S.A.):
The Global Organization for Multi-Vendor Integration Protocol (GO-MVIP) 3220 N Street NW, Suite 360 Washington, DC 20007 Tel: Tel: Fax: Web: (800) 669-6857 (within U.S.A.) (903) 769-3717 (outside U.S.A.) (903) 769-3818 www.mvip.org
ITU-T (International):
Publication Services of International Telecommunication Union Telecommunication Standardization Sector Place des Nations, CH 1211 Geneve 20, Switzerland Tel: 22 730 5852 Fax: 22 730 5853 Web: www.itu.int
JEDEC (International):
Joint Electron Device Engineering Council 2500 Wilson Boulevard Arlington, VA 22201-3834 Tel: (703) 907-7559 Fax: (703) 907-7583 Web: www.jedec.org
MIL-STD (U.S.A.):
DODSSP Standardization Documents Ordering Desk Building 4 / Section D 700 Robbins Avenue Philadelphia, PA 19111-5094 Tel: (215) 697-2179 Fax: (215) 697-1462 Web: www.dodssp.daps.mil
PCI SIG (U.S.A.):
PCI Special Interest Group 5440 SW Westgate Dr., #217 Portland, OR 97221 Tel: Tel: Fax: Web: (800) 433-5177 (within U.S.A.) (503) 291-2569 (outside U.S.A.) (503) 297-1090 www.pcisig.com
Telcordia (U.S.A.):
Telcordia Technologies, Inc. Attention - Customer Service 8 Corporate Place Rm 3A184 Piscataway, NJ 08854-4157 Tel: Tel: Fax: Web: (800) 521-2673 (within U.S.A.) (732) 699-2000 (outside U.S.A.) (732) 336-2559 www.telcordia.com
TTC (Japan):
TTC Standard Publishing Group of the Telecommunication Technology Committee Hamamatsu-cho Suzuki Building 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp
- 93 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TL3M TXC-03453B
DATA SHEET
LIST OF DATA SHEET CHANGES
This change list identifies those areas within this updated PRELIMINARY TL3M TXC-03453B Edition 3 Data Sheet that have significant differences relative to the previous and now superseded PRELIMINARY TL3M TXC-03453B Edition 2 Data Sheet: Updated TL3M TXC-03453B Data Sheet: PRELIMINARY Edition 3, September 2003. Previous TL3M TXC-03453B Data Sheet: PRELIMINARY Edition 2, June 2002.
The page numbers indicated below of this updated TXC-03453B Edition 3 Data Sheet include significant changes relative to the previous TXC-03453B Edition 2 Data Sheet. Page Number of Updated Data Sheet All 1 15 26 30 31
Summary of the Change
Changed document number, edition number and date. Added Patent number on the bottom left corner. Corrected diagram of Figure 6 at D1 and E1. Changed Name/Function for Symbols VRS1, SBS1, GRS1, VRS2, SBS2 and GRS2 Deleted Max value and added Min value for parameter IOL in the "OUTPUT PARAMETERS FOR LVCMOS 4mA'' table. Deleted Max values and added Min values for parameter IOL in the "OUTPUT PARAMETERS FOR LVCMOS 8mA'' and "INPUT/OUTPUT PARAMETERS FOR LVTTL/LVCMOS 8mA'' tables. Changed diagram of Figure 28. Added Note 5 for Figure 29. Added Note 5 for Figure 30. Changed Bits 7-4 at Address 0F3H. Changed Bits 7-4 at Address XF3H. Changed Bit 4 at Address XF4H. Changed second sentence of Description paragraph. Changed Description for Symbol ROVFL. Changed Description for Symbol LOVFL. Changed "Standards Documentation Sources'' section. Changed "List of Data Sheet Changes'' section.
51 52 53 62 63 81 82 92 94
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
- 94 of 96 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TL3M TXC-03453B
-NOTES-
TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
PRELIMINARY information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. Characteristic data and other specifications are subject to change. Contact TranSwitch Applications Engineering for current information on this product.
- 95 of 96 -
PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003
TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com

▲Up To Search▲

Price & Availability of TXC-03453B

	To Download TXC-03453B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .